A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.
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Jan 17, 2022 - VHDL
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harvard-architecture-processor
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Implementation of Harvard Architecture Processor using VHDL
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Feb 19, 2021 - VHDL
A multi-cycle CPU which supports 54 Mips instructions
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Jul 13, 2023 - Verilog
A 32-bit single cycle RISC CPU based on Harvard architecture with no cache or pipeline, by having very simple and reduced instruction set it can be used for educational purpose.
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Jun 22, 2022 - Verilog
A VHDL design of a simple custom processor, designed as a project for the Structure of Computer Systems class // 3rd year, 1st semester @ TUCN
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Feb 16, 2022 - VHDL
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