instruction-level-parallelism

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Here are 9 public repositories matching this topic...

sdasgup3 / parallel-processor-design

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Super scalar Processor design

Updated Sep 7, 2014
Verilog

SIMDE-ULL / SIMDE

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Educational computer simulator on a mission to "superscalate" the study of computer architecture fundamentals

simulator educational learning-by-doing pipelining computer-architecture risc out-of-order superscalar learning-resources instruction-level-parallelism computer-architecture-and-organization

Updated Nov 11, 2024
TypeScript

w-feng / CompArch-MIPS-POWER

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Curriculum material for teaching computer architecture with MIPS and POWER

cpu memory gpu architecture pedagogy computer-architecture computer-organization instruction-level-parallelism thread-level-parallelism data-level-parallelism

Updated Feb 10, 2024
Python

CSpyridakis / Tomasulo

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Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm

pipeline architecture vhdl computer-architecture pipeline-processor out-of-order tomasulo instruction-level-parallelism tomasulo-algorithm

Updated Mar 24, 2019
VHDL

dominiksalvet / super-riscv

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Superscalar dual-issue RISC-V processor

open-source pipeline core rtl forwarding systemverilog gtkwave testbench superscalar in-order risc-v microarchitecture low-power verilator ahb3-lite instruction-level-parallelism dual-issue riscv-gcc

Updated Jul 31, 2024
SystemVerilog

gocho1307 / Labs-OC

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Project for 2023/2024 - Computer Organization @ IST

cache university-project pipelining instruction-level-parallelism

Updated Oct 28, 2023
C

sid-xyz / RNBIP_Pipelined-Microprocessor

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Redesigned the RNBIP single-bus architecture to implement a 3 stage instruction-level pipeline.

fpga architecture microprocessor academic-project instruction-set-architecture instruction-level-parallelism

Updated Sep 25, 2020
Verilog

sebastian-wardzinski / computer-architecture

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ECE552: Computer Architecture — Fall 2020.

multithreading computer-architecture branch-prediction cache-coherence cache-optimization instruction-level-parallelism memory-consistency dynamic-scheduling control-hazards data-hazards multiprocessor-systems superscalar-cpu

Updated Dec 28, 2021
C

scicomp-durham / comp3577-mimd-code

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Examples of OpenMP for instruction-level parallelism.

openmp instruction-level-parallelism mimd

Updated Dec 8, 2022
C

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instruction-level-parallelism

Here are 9 public repositories matching this topic...

sdasgup3 / parallel-processor-design

SIMDE-ULL / SIMDE

w-feng / CompArch-MIPS-POWER

CSpyridakis / Tomasulo

dominiksalvet / super-riscv

gocho1307 / Labs-OC

sid-xyz / RNBIP_Pipelined-Microprocessor

sebastian-wardzinski / computer-architecture

scicomp-durham / comp3577-mimd-code

Improve this page

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