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memory-controller

Here are 8 public repositories matching this topic...

AngeloJacobo / UberDDR3

Opensource DDR3 Controller

fpga controller verilog phy ddr3 memory-controller ddr3-controller ddr3-phy

Updated Nov 3, 2024
Verilog

someone755 / ddr3-controller

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

fpga verilog ddr3 memory-controller

Updated Dec 1, 2022
Verilog

Elphel / eddr3

mirror of https://git.elphel.com/Elphel/eddr3

fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

Updated Oct 16, 2017
Verilog

krzk / linux

This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).

Updated Nov 3, 2024
C

FlorianFrank / verilog-baremetal-sram-controller

A bare-metal SRAM memory controller suitable for Xilinx FPGAs.

fpga verilog sram xilinx memory-controller

Updated Jan 15, 2024
Verilog

teekamkhandelwal / SRAM_Controller

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

memory verilog sram memory-management vivado questasim sdram sdram-controller memory-controller verilog-project vlsi-design sram-controller sram-controller-advanced sram-features-power-security-brust verlog-hdl enhanched-sram-controller

Updated Oct 21, 2024
Verilog

yasnakateb / SdramController

🛠 A SDRAM controller in Verilog HDL

verilog icarus-verilog verilog-hdl iverilog sdram sdram-controller memory-controller

Updated Mar 21, 2022
Verilog

jtsimons / DRAMC

Behavioral architecture of a read/write cycle controller for a DRAM chip.

fpga vhdl tcl dram digital-design memory-controller memory-design

Updated May 26, 2023
VHDL

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