AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

A Chisel RTL generator for network-on-chip interconnects

Network on Chip Implementation written in SytemVerilog

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

HLS for Networks-on-Chip

Ratatoskr NoC Simulator

System-on-Chip Interconnection Network - Simulation Environment (front-end)

HLS code for Network on Chip (NoC)

Development and simulation framework for Application Specific Vector Processor

My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA

Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research

Fork of the gem5 simulator with Garnet2.0 and DSENT extensions

RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.

A Voting Approach for Adaptive Network-on-Chip Power-Gating

A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs

System-on-Chip Interconnect Network Simulation Environment back-end (simulator)

In this project, I investigate and design a NoC system consisting of the router/switch, IPs (CPU or other hardware module), and interconnection structure (topology) such as Mesh.

A Network-on-Chip for the System-of-Systems Era, Enabling mixed interface communication between embedded devices (MCU, sensors etc.) over a common protcol stack