Time to Digital Converter on an FPGA

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board

Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board.

Mini projects based on Xilinx Nexys 4 DDR

My experiments with Nexys4 DDR Artix-7 FPGA Board

Xilinx Vivado Project

Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs

An audio project with the NEXYS 4 ddr

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

FPGA based SD card reads and displays pictures and performs digital recognition experiments.

A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board

It is my Final Degree Project of Grado de Tecnologías y Servicios de Telecomunicación in Universidad Politécnica de Madrid

An FPGA implementation of Cummings' Asynchronous FIFO

VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.

CECS 490A/490B Course; Senior Project Design

Nexys 4 DDR - Rom Controller

Using the FPGA board Nexys Artix-7 to design a breakout game with vhdl language.

Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU

A stopwatch on Digilent Nexys4 DDR written in Verilog