An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.

Register file cache implementation on the Marssx86 architectural simulator

Basic Implementation of Tomasulo Algorithm, with memory unit pipelined.

Go implementation of a bitmap ring-buffer which tracks the state of windowed out-of-order processing over a sequence of logical offsets

Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

2-way Out of Order RISC-V Processor

This repository contains the Labs done in the course COL718 High Performance Computing taught by Prof. Sourav Bansal at IIT, Delhi in Fall 2019

A Flink library to implement both a buffer-based and a speculative out-of-order event arrival handlers for online process discovery

Keyed Watermarks in Apache Flink

try to design a Single_Emission_Out-of-Order_Pipeline_RISC-V_Processor

EdgeMailer is a tool that tests rate limits of mail providers, it uses libcurl and libuv to make concomitant assynchronous request. This tool is outdated and now is closed source and belongs to YouSendr.

Superscalar OoO RISCV processor written in Chisel

CENOS: The Modern CPU Simulator

Introduction in Dynamic Instruction Scheduling (Advanced Computer Architecture) implementing Tomasulo's Algorithm

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022

An approach to apply concept drifts and ADWIN on the streams event time to reason about the progress of watermarks

Educational computer simulator on a mission to "superscalate" the study of computer architecture fundamentals

A compiler, assembler, and processor.

Advanced Architecture Labs with CVA6