Mensajea automáticamente a los usuarios en un tablón de idealista
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Oct 13, 2021 - Python
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piso
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In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will get the serial output from the right most D flip-flop.
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Jul 25, 2021 - Verilog
This repository contain all the necessary files to verify PISO Universal Register
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Jan 28, 2024 - SystemVerilog
C-library to interface with shiftregisters on the Raspberry Pi Pico (or compatible boards)
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Aug 15, 2024 - C
The shift register, which allows parallel input (data is given separately to each flip flop and in a simultaneous manner) and produces a serial output is known as Parallel-In Serial-Out shift register.
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Jul 25, 2021 - Verilog
basic implementation of logic structures using verilog (revising github)
registers
pipo
d-flipflop
full-adder
sipo
sequence-detector
siso
piso
verilog-testbenches
synchronous-counter
priority-encoder
jk-flipflop
t-flipflop
sr-flip-flop
full-subtractor
half-subtractor
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Feb 29, 2024 - Verilog
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