processor-design
Here are 71 public repositories matching this topic...
A CPU implemented in a modular synthesizer
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Mar 20, 2022
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
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Jul 17, 2022 - Verilog
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
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Jul 14, 2021 - SystemVerilog
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
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Dec 7, 2024 - Verilog
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
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Jun 19, 2021 - VHDL
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
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Dec 18, 2024 - SystemVerilog
Chisel implementation of Neural Processing Unit for System on the Chip
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Oct 28, 2024 - Scala
EE577b-Course-Project
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May 6, 2020 - Verilog
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
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Mar 13, 2024 - C
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
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Apr 23, 2023 - VHDL
Domain Specific Hardware Accelerators - VLSI CAD Project
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Jan 11, 2021 - Bluespec
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
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Aug 31, 2021 - Assembly
NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs
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Jan 8, 2024 - Go
A simple processor designed using Verilog and Altera DE1 development board.
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Apr 22, 2020 - Verilog
An 8-bit processor in VHDL based on a simple instruction set
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Mar 7, 2019 - VHDL
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
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Apr 29, 2022 - Python
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