NTUEE Digital Circuit Lab 24Fall

2019年UPC应用物理专业《数字电子技术课程设计》任务内容：数字时钟设计

Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II

Arilla - a RISC-V based microcomputer system, with a PS2 mouse controller and 12-bit RGB SVGA graphics card, running Arilla Paint.

Verilog Implementation of the LC-3 Processor. DA CS 603

Ejemplos de codigo con implementación en hardware para la tarjeta Cyclone IV lenguaje VHDL

FIR filter for Altera DE0 EP3C16F484C6N Created on top of SURF VHDL FIR Filter

Logic Design.

Bizzas CPU design

DEUARC RISC computer design in Quartus II 13.0

Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.

The goal of ECE 385 course is to teach students to design, build, and test/debug a digital system, which can be a 16-bit microprocessor, a dedicated logic core, or a system-on-a-chip (SoC) platform

Assorted Verilog that brings up different elements (VGA, Ethernet, Switches, LED, LCD, etc.) of the terasIC DE2-70 Development Board.

This space ship game project, where the spaceship is positioned at the center and objects coming from different directions can be hit using FPGA buttons, has been implemented with Verilog coding in quartus environment for Altera System-on-Chip (SoC) FPGA and VGA for display.

CWRU's Logic Lab

A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.

Projeto de uma ULA feito em Quartus II para a disciplina de Sistemas Digitais (2019.1)

Implementações feitas em VHDL nas disciplinas de Circuitos Digitais I, Circuitos Digitais II e Sistemas Digitais Avançados

Quartus II Pipelined Processor

Prácticas de la asignatura de Desarrollo de Hardware Digital en la UGR