A library to support multiple shift registers, SIPOs, as a continuous array and in banks of registers
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Updated
Jun 2, 2022 - C++
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shift-registers
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This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.
logic-gates
icarus-verilog
hdl
multiplexer
decoders
encoders
combinational-circuit
adders
sequential-circuits
flip-flops
arithmetic-circuits
demultiplexer
ripple-carry-adder
shift-registers
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Updated
Jul 15, 2024 - Verilog
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