SnrNotHere16 / RISCVSingleCycleProcessor Star 8 Code Issues Pull requests A RISC-V Single Cycle Processor which is done in verilog. module verilog vivado computer-architecture risc-v 32-bit hardware-description-language riscv32 risc-architecture-processor single-cycle-processor testbench-generator-verilog Updated Jul 20, 2020 Verilog
phillbush / tbgen Star 2 Code Issues Pull requests Testbench generator in AWK for Verilog modules awk verilog testbench testbench-generator-verilog testbench-generator Updated Aug 19, 2021 Shell
Stenardt-9002 / Verilog-files-VLSI-course- Star 2 Code Issues Pull requests verilog files verilog wallace-tree-multiplier floating-point-multiplication floating-point-adder recursion-doubling testbench-generator-verilog Updated Jun 22, 2020 Verilog
jElhamm / Verilog-HDL-Codes-Collection Star 0 Code Issues Pull requests "Repository containing a collection of Verilog code modules and test bench for digital design projects. " counter encoder decoder verilog alu multiplexer comparator testbench verilog-hdl gates 7segment shiftregister verilog-programs verilog-simulator verilog-project testbench-generator-verilog Updated Apr 1, 2024 Verilog
0marAmr / Testbench-Generator Star 0 Code Issues Pull requests python verilog testbench verilog-hdl testbench-generator-verilog Updated Mar 14, 2023 Python
Kerolos-Noshy / verilog_testbench_generator Star 0 Code Issues Pull requests Python script for generating a Verilog testbench (University Project) gui verilog testbench-generator-verilog Updated Jul 20, 2023 Jupyter Notebook