cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Fun, portable, minimalistic virtual machine.

Functional verification project for the CORE-V family of RISC-V cores.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

AMBA AXI VIP

Code generation tool for control and status registers

Awesome ASIC design verification

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Network on Chip Implementation written in SytemVerilog

VIP for AXI Protocol

Control and status register code generator toolchain

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

A Framework for Design and Verification of Image Processing Applications using UVM

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

🐌Yet Another Simulation Architecture

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

Generate UVM register model from compiled SystemRDL input