A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.
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Aug 3, 2020 - Verilog
A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.
单周期、多周期CPU(Verilog/武汉大学计算机学院计组实验)
A small CPU / ISA and a testbench that displays its instructions' equivalent in assembly&machine language.
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