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victim-cache

Here are 3 public repositories matching this topic...

avikram2 / RISCVPipelinedProcessor

Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.

cache riscv32 victim-cache pipelined-processors set-associative-cache pipelined-risc

Updated Dec 23, 2022
Verilog

pkashyap95 / CacheSimulator

Cache simulator using that is configureable for L1, L1+L2, L1 (VC), L1(VC)+L2

java simulator cache lru-cache victim-cache miroarchitecture

Updated Oct 24, 2018
Java

ArmaghanSarvar / Cache-simulation

Computer Architecture course project

computer-architecture cache-simulator victim-cache

Updated Jan 26, 2021
Java

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