vivado-simulator

Here are 14 public repositories matching this topic...

suoto / hdl_checker

Repurposing existing HDL tools to help writing better code

Updated Jun 6, 2024
Python

Arjun-Narula / Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

wyvernSemi / mem_model

Star

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

Updated Nov 20, 2024
VHDL

esynr3z / pyhdlsim

Star

Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

Updated Jan 17, 2021
Python

mzh330521 / SublimeLinter-contrib-xsim

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Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

sublime-text vhdl sublimelinter linter-plugin verilog systemverilog xsim vivado-simulator

Updated May 29, 2024
Python

RipperJ / VerilogExpr2NAND-NOR

Star

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

compiler simulation lex espresso ply verilog yacc boolean-expression nand logic-minimization nor xsim vivado-simulator pyeda

Updated Jun 4, 2023
Python

arhamhashmi01 / Axi4-lite

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This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

systemverilog hardware-designs verilator axi4-lite axi4-protocol vivado-simulator axi4-lite-interface

Updated May 4, 2024
SystemVerilog

Ammar-Bin-Amir / SystemVerilog_Practice

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Practice Codes of SystemVerilog Language

vscode systemverilog vivado-simulator

Updated May 19, 2024
SystemVerilog

amirah-sri / all_verilog

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I am trying to develop my skills through daily practice and consistency.

verilog vivado vlsi verilog-hdl verilog-programs verilog-project verilog-code vivado-simulator

Updated Jul 31, 2024
Verilog

bp0609 / Mini-Processor-Verilog-FPGA-Implemented

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This repo contains a mini-processor design implemented on FPGA using verilog

verilog fpga-board vivado-simulator

Updated May 27, 2024
Verilog

WimukthiMadushan / Computer-Organization-and-Digital-Design

Star

Includes lab exercises from my Computer Organization and Digital Design module. It features implementations of various components inside a processor using VHDL . Finally I make 4 bit nanoprocessor combining all components those build in previous labs.

vhdl vivado vhdl-code vivado-simulator nanoprocessor