Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
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Updated
Oct 8, 2023 - C++
Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Gatery, a library for circuit design.
This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Spiking Neural Network Accelerator
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
Combinatorial and Decision Making Optimization (CDMO) project during the A.Y. 2021/2022.
This repo contains golden vector and randomization testbenches for SRAM module.
Domain Specific Hardware Accelerators - VLSI CAD Project
Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
FuzzyMSFLA-Algorithm (Fuzzy adaptive optimisation method)
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