Simple CPU Design in Verilog with MIPS-like Architecture, featuring Branch Prediction and Interrupt Control.
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Updated
Sep 9, 2024
Simple CPU Design in Verilog with MIPS-like Architecture, featuring Branch Prediction and Interrupt Control.
Implementation of a model of pipelined MIPS processor in Verilog
Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4
saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)
UART implementation using Verilog HDL
This repository contains VHDL codes for a 16 bit binary square root computer module.
🖼✏️ My first baby steps into the world of image processing
Design and Implementation of Arithmetic Logic Unit Capable of Calculating Z=1/4(A X B)+1
Running your application from DDR memory & BPI flash using SREC bootloader
These are VHDL codes that I wrote as a part of our Computer Architecture Course in the 4th Semester.
In the repository I have implemented a ALU with Finite State machine with VHDL and Xilinx ISE 14.7 application. Also a BCD to seven segment have been implemented for input and output digits.
VHDL Verilog / Clock on Spartan3 / 2014 University of Seoul
RISC22 is a simple 22-bit RISC CPU designed in VHDL, featuring a minimal instruction set and a pipelined architecture for efficient execution.
This repository contains three different design of binary multiplier. Array Multiplier, Carry Save Multiplier and normal multiplier.
arctan and exponential functions has been implemented with Cordic IP core in Xilinx ISE14.6.
Binary Clock adapted for Papilio One 500K. Show hours, minutes and seconds using binary system
Project for Computer Design course.
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