CMake for Xilinx Vivado/Vitis
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Jun 13, 2023 - CMake
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xilinx-vitis
Here are 13 public repositories matching this topic...
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
embedded
fpga
hls
xilinx
vivado
xilinx-fpga
basys3
xilinx-vivado
axi
artix
axi-stream
vivado-ip-integrator
artix-7
xilinx-hls
vitis
axi-lite
xilinx-vitis
vivado-vitis
vitis-hls
axi-memory-mapped
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Nov 21, 2023 - TeX
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
embedded
fpga
hls
xilinx
vivado
xilinx-fpga
basys3
xilinx-vivado
microblaze
axi
artix
axi-stream
vivado-ip-integrator
artix-7
xilinx-hls
vitis
axi-lite
xilinx-vitis
vivado-vitis
vitis-hls
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Dec 3, 2023 - C
🔖 Downgrade to 2019.2
fpga
aur
archlinux
arch
arch-linux
xilinx
vivado
aur-packages
xilinx-fpga
xilinx-vivado
fpga-programming
vitis
vivado-installer
xilinx-vitis
vivado-vitis
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Dec 25, 2023 - Shell
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
zynq
xilinx
xilinx-fpga
zynq-7010
xilinx-vivado
zynq-7000
xilinx-sdk
xilinx-zynq
zynq-example-project
zynq-7020
xilinx-vitis
zynq-ultrascale
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Mar 6, 2024 - C
Carry-Lookahead 16-bits Adder (CLA16) computes sums by rapidly determining carry bits through parallel processing.
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Mar 14, 2024 - C++
A TFTP server running on Zynq-7000
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May 15, 2024 - C
Canny edge detection in HLS
hls
xilinx
pynq-hardware-overlay
canny-edge-detection
xilinx-fpga
xilinx-vivado
high-level-synthesis
pynq-z2
xilinx-vitis
pynq-board
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Jun 28, 2024 - Jupyter Notebook
FPGA-based hardware-accelerated, parallelized, and highly optimized solution for solving the Travelling Salesperson Problem (TSP) using Xilinx Zynq-7000 on a Digilent Zybo Z7-10 board, featuring FreeRTOS for real-time task management.
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Aug 15, 2024 - C
Comprehensive open-source curriculum for mastering heterogeneous computing architectures and optimization.
xilinx
heterogeneous-parallel-programming
xilinx-fpga
xilinx-vivado
xilinx-zynq
xilinx-hls
xilinx-vitis
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Sep 19, 2024 - C
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
llvm
clang
xilinx-fpga
sycl
cpp20
accelerators
xilinx-vitis
trisycl
oneapi-dpc
sycl-compilation
dpc-toolchain
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Nov 4, 2024 - C++
Xilinx Tools Tutorials
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Nov 12, 2024 - C++
HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
bioinformatics
fpga
hls
dynamic-programming
hardware-acceleration
fpga-accelerator
high-level-synthesis
xilinx-vitis
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Updated
Nov 12, 2024 - C++
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