From a11daea2c4ca9e77e6dd8aa96266c3e5c6a68dc7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Luis=20Panadero=20Guarde=C3=B1o?= Date: Thu, 19 Feb 2015 19:36:18 +0100 Subject: [PATCH] Sync CPU specs to v0.4.2 Correct cyclecount to v0.4.1 ~ v0.4.2 --- src/tr3200/tr3200.cpp | 2 +- src/tr3200/tr3200_cycles.inc | 8 ++++---- src/tr3200/tr3200_opcodes.hpp | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/tr3200/tr3200.cpp b/src/tr3200/tr3200.cpp index 4eb1b57..b5a9d06 100644 --- a/src/tr3200/tr3200.cpp +++ b/src/tr3200/tr3200.cpp @@ -3,7 +3,7 @@ * \file tr3200.cpp * \copyright LGPL v3 * - * Implementation of the TR3200 CPU v0.3.0 + * Implementation of the TR3200 CPU v0.4.2 * @see https://github.com/trillek-team/trillek-computer/blob/master/TR3200.md */ diff --git a/src/tr3200/tr3200_cycles.inc b/src/tr3200/tr3200_cycles.inc index 7096f9f..8801bc6 100644 --- a/src/tr3200/tr3200_cycles.inc +++ b/src/tr3200/tr3200_cycles.inc @@ -1,14 +1,14 @@ // Look-uptable for cycle counts in function of OpCode - +// v 0.4.2 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 1, 4, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0x1X 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0x1X 3, 3, 3, 3, 3, 3, 4, 3, 4, 6, 1, 1, 1, 1, 1, 1, // 0x2X 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0x3X - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // 0x4X - 3, 3, 3, 3, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0x5X + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 1, 1, 1, // 0x4X + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0x5X 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0x6X - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0x7X + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, // 0x7X 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 20, // 0x8X 30, 25, 35, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, // 0x9X 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0xAX diff --git a/src/tr3200/tr3200_opcodes.hpp b/src/tr3200/tr3200_opcodes.hpp index f1cbbc3..5e98c72 100644 --- a/src/tr3200/tr3200_opcodes.hpp +++ b/src/tr3200/tr3200_opcodes.hpp @@ -3,7 +3,7 @@ * \file TR3200_opcodes.hpp * \copyright LGPL v3 * - * OpCodes of TR3200 CPU v0.4.0 + * OpCodes of TR3200 CPU v0.4.2 * @see https://github.com/trillek-team/trillek-computer/blob/master/TR3200.md */ #ifndef __TR3200_OPCODES_HPP_