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RVF.core_desc
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RVF.core_desc
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import "RVI.core_desc"
// TODO: review instruction description wrt. Spec after type system is fixed
InstructionSet RV32F extends Zicsr {
architectural_state {
unsigned<32> FLEN = 32;
unsigned<32> FFLAG_MASK = 0x1f;
register unsigned<FLEN> F[32];
unsigned<XLEN>& FCSR = CSR[RV_CSR_FCSR];
}
functions {
extern unsigned<32> fadd_s(unsigned<32>, unsigned<32>, unsigned char); //fail
extern unsigned<32> fsub_s(unsigned<32>, unsigned<32>, unsigned char);
extern unsigned<32> fmul_s(unsigned<32>, unsigned<32>, unsigned char);
extern unsigned<32> fdiv_s(unsigned<32>, unsigned<32>, unsigned char);
extern unsigned<32> fmadd_s(unsigned<32>, unsigned<32>, unsigned<32>, unsigned<32>, unsigned char);
extern unsigned<32> fsel_s(unsigned<32>, unsigned<32>, unsigned<32>);
extern unsigned<32> fsqrt_s(unsigned<32>, unsigned char);
extern unsigned<32> fcmp_s(unsigned<32>, unsigned<32>, unsigned<32>);
extern unsigned<32> fcvt_s(unsigned<32>, unsigned<32>, unsigned char); //fail
extern unsigned<64> fcvt_32_64(unsigned<32>, unsigned<32>, unsigned char); //fcvt_w fails
extern unsigned<32> fcvt_64_32(unsigned<64>, unsigned<32>, unsigned char);
extern unsigned<32> unbox_s(unsigned<64>);
extern unsigned<32> fclass_s(unsigned<32>);
extern unsigned<32> fget_flags();
unsigned<3> get_rm(unsigned<3> rm) {
if (rm == 7) rm = FCSR[7:5];
if (rm > 4) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION);
return rm;
}
}
instructions {
FLW {
encoding: imm[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000111;
assembly:"f {rd}, {imm}({name(rs1)})";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS] + (signed<12>)imm;
unsigned<32> res = (unsigned<32>)MEM[offs];
if (FLEN == 32)
F[rd] = res;
else { // NaN boxing
F[rd] = ((signed<FLEN>)-1 << 32) | (unsigned<FLEN>)res;
}
}
}
FSW {
encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm[4:0] :: 7'b0100111;
assembly:"f {rs2}, {imm}({name(rs1)])";
behavior: {
unsigned<XLEN> offs = X[rs1 % RFS] + (signed<12>)imm;
MEM[offs] = (unsigned<32>)F[rs2];
}
}
FMADD_S {
encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1000011;
assembly:"{name(rm)}, {name(rd)}, f {rs1}, f {rs2}, f {rs3}";
behavior: {
//F[rd]f = F[rs1]f * F[rs2]f + F[rs3]f;
if (FLEN == 32)
F[rd] = fmadd_s(F[rs1], F[rs2], F[rs3], 0, get_rm(rm));
else { // NaN boxing
unsigned<32> res = fmadd_s(unbox_s(F[rs1]), unbox_s(F[rs2]), unbox_s(F[rs3]), 0, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FMSUB_S {
encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1000111;
assembly:"{name(rm)}, {name(rd)}, f {rs1}, f {rs2}, f {rs3}";
behavior: {
//F[rd]f = F[rs1]f * F[rs2]f - F[rs3]f;
if (FLEN == 32)
F[rd] = fmadd_s(F[rs1], F[rs2], F[rs3], 1, get_rm(rm));
else { // NaN boxing
unsigned<32> res = fmadd_s(unbox_s(F[rs1]), unbox_s(F[rs2]), unbox_s(F[rs3]), 1, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FNMADD_S {
encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1001111;
assembly:"{name(rm)}, name(rd), f {rs1}, f {rs2}, f {rs3}";
behavior: {
//F[rd]f = -F[rs1]f * F[rs2]f + F[rs3]f;
if (FLEN == 32)
F[rd] = fmadd_s(F[rs1], F[rs2], F[rs3], 2, get_rm(rm));
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> frs3 = unbox_s(F[rs3]);
unsigned<32> res = fmadd_s(frs1, frs2, frs3, 2, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FNMSUB_S {
encoding: rs3[4:0] :: 2'b00 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1001011;
assembly:"{name(rm)}, {name(rd)}, f {rs1}, f {rs2}, f {rs3}";
behavior: {
//F[rd]f = -F[rs1]f * F[rs2]f - F[rs3]f;
if (FLEN == 32)
F[rd] = fmadd_s(F[rs1], F[rs2], F[rs3], 3, get_rm(rm));
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> frs3 = unbox_s(F[rs3]);
unsigned<32> res = fmadd_s(frs1, frs2, frs3, 3, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FADD_S {
encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, f {rs1}, f {rs2}";
behavior: {
// F[rd]f = F[rs1]f + F[rs2]f;
if (FLEN == 32)
F[rd] = fadd_s(F[rs1], F[rs2], get_rm(rm));
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = fadd_s(frs1, frs2, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FSUB_S {
encoding: 7'b0000100 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, f {rs1}, f {rs2}";
behavior: {
// F[rd]f = F[rs1]f - F[rs2]f;
if (FLEN == 32)
F[rd] = fsub_s(F[rs1], F[rs2], get_rm(rm));
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = fsub_s(frs1, frs2, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FMUL_S {
encoding: 7'b0001000 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, f {rs1}, f {rs2}";
behavior: {
// F[rd]f = F[rs1]f * F[rs2]f;
if (FLEN == 32)
F[rd] = fmul_s(F[rs1], F[rs2], get_rm(rm));
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = fmul_s(frs1, frs2, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FDIV_S {
encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, f {rs1}, f {rs2}";
behavior: {
// F[rd]f = F[rs1]f / F[rs2]f;
if (FLEN == 32)
F[rd] = fdiv_s(F[rs1], F[rs2], get_rm(rm));
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = fdiv_s(frs1, frs2, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FSQRT_S {
encoding: 7'b0101100 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, f {rs1}";
behavior: {
//F[rd]f = sqrt(F[rs1]f);
if (FLEN == 32)
F[rd] = fsqrt_s(F[rs1], get_rm(rm));
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> res = fsqrt_s(frs1, get_rm(rm));
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FSGNJ_S {
encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
assembly:"f {rd}, f {rs1}, f {rs2}";
behavior: {
if (FLEN == 32)
F[rd] = F[rs2][31:31] :: F[rs1][30:0];
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = frs2[31:31] :: frs1[30:0];
F[rd] = (-1 << 32) | (unsigned<FLEN>)res;
}
}
}
FSGNJN_S {
encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
assembly:"f {rd}, f {rs1}, f {rs2}";
behavior: {
if (FLEN == 32)
F[rd] = ~F[rs2][31:31] :: F[rs1][30:0];
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = ~frs2[31:31] :: frs1[30:0];
F[rd] = (-1 << 32) | (unsigned<FLEN>)res;
}
}
}
FSGNJX_S {
encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1010011;
assembly:"f {rd}, f {rs1}, f {rs2}";
behavior: {
if (FLEN == 32)
F[rd] = F[rs1] ^ (F[rs2] & 0x80000000);
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = frs1 ^ (frs2 & 0x80000000);
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
}
}
FMIN_S {
encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
assembly:"f {rd}, f {rs1}, f {rs2}";
behavior: {
//F[rd]f = choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
if (FLEN == 32)
F[rd] = fsel_s(F[rs1], F[rs2], 0);
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = fsel_s(frs1, frs2, 0);
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FMAX_S {
encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
assembly:"f {rd}, f {rs1}, f {rs2}";
behavior: {
//F[rd]f = choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
if (FLEN == 32)
F[rd] = fsel_s(F[rs1], F[rs2], 1);
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
unsigned<32> res = fsel_s(frs1, frs2, 1);
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FCVT_W_S {
encoding: 7'b1100000 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, {name(rd)}, f {rs1}";
behavior: {
signed<32> res = 0;
if (FLEN == 32)
res = fcvt_s(F[rs1], 0, rm);
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
res = fcvt_s(frs1, 0, rm);
}
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FCVT_WU_S {
encoding: 7'b1100000 :: 5'b00001 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, {name(rd)}, f {rs1}";
behavior: {
//FIXME: according to the spec it should be zero-extended not sign extended
unsigned<32> res = 0;
if (FLEN == 32)
res = fcvt_s(F[rs1], 1, rm);
else { // NaN boxing
unsigned<32> frs1 = unbox_s(F[rs1]);
res = fcvt_s(frs1, 1, rm);
}
if ((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)(signed)res;
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FEQ_S {
encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1010011;
assembly:"{name(rd)}, f {rs1}, f {rs2}";
behavior: {
unsigned<32> res = 0;
if (FLEN == 32)
res = fcmp_s(F[rs1], F[rs2], 0);
else {
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
res = fcmp_s(frs1, frs2, 0);
}
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FLT_S {
encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
assembly:"{name(rd)}, f {rs1}, f {rs2}";
behavior: {
unsigned<32> res = 0;
if (FLEN == 32)
res = fcmp_s(F[rs1], F[rs2], 2);
else {
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
res = fcmp_s(frs1, frs2, 2);
}
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FLE_S {
encoding: 7'b1010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
assembly:"{name(rd)}, f {rs1}, f {rs2}";
behavior: {
unsigned<32> res = 0;
if (FLEN == 32)
res = fcmp_s(F[rs1], F[rs2], 1);
else {
unsigned<32> frs1 = unbox_s(F[rs1]);
unsigned<32> frs2 = unbox_s(F[rs2]);
res = fcmp_s(frs1, frs2, 1);
}
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FCLASS_S {
encoding: 7'b1110000 :: 5'b00000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1010011;
assembly:"{name(rd)}, f {rs1}";
behavior: {
unsigned<32> res = 0;
if (FLEN == 32)
res = fclass_s(F[rs1]);
else
res = fclass_s(unbox_s(F[rs1]));
if ((rd % RFS) != 0) X[rd % RFS] = res;
}
}
FCVT_S_W {
encoding: 7'b1101000 :: 5'b00000 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, {name(rs1)}";
behavior: {
if (FLEN == 32)
F[rd] = fcvt_s((unsigned)X[rs1 % RFS], 2, rm);
else { // NaN boxing
unsigned<32> res = fcvt_s((unsigned)X[rs1 % RFS], 2, rm);
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
}
}
FCVT_S_WU {
encoding: 7'b1101000 :: 5'b00001 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, {name(rs1)}";
behavior: {
if (FLEN == 32)
F[rd] = fcvt_s((unsigned)X[rs1 % RFS], 3, rm);
else { // NaN boxing
unsigned<32> res = fcvt_s((unsigned)X[rs1 % RFS], 3, rm);
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
}
}
FMV_X_W {
encoding: 7'b1110000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
assembly:"{name(rd)}, f {rs1}";
behavior: {
if ((rd % RFS) != 0) X[rd % RFS] = (unsigned<XLEN>)(signed<32>)F[rs1];
}
}
FMV_W_X {
encoding: 7'b1111000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1010011;
assembly:"f {rd}, {name(rs1)}";
behavior: {
if (FLEN == 32)
F[rd] = X[rs1 % RFS];
else { // NaN boxing
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)X[rs1 % RFS];
}
}
}
}
}
InstructionSet RV64F extends RV32F {
instructions {
FCVT_L_S { // fp to 64bit signed integer
encoding: 7'b1100000 :: 5'b00010 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, {name(rd)}, f {rs1}";
behavior: {
signed<64> res = fcvt_32_64(unbox_s(F[rs1]), 0, rm);
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FCVT_LU_S { // fp to 64bit unsigned integer
encoding: 7'b1100000 :: 5'b00011 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, {name(rd)}, f {rs1}";
behavior: {
unsigned<64> res = fcvt_32_64(unbox_s(F[rs1]), 1, rm);
if ((rd % RFS) != 0) X[rd % RFS] = res;
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
FCVT_S_L { // 64bit signed int to to fp
encoding: 7'b1101000 :: 5'b00010 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, {name(rs1)}";
behavior: {
unsigned<32> res = fcvt_64_32(X[rs1 % RFS], 2, rm);
if (FLEN == 32)
F[rd] = res;
else { // NaN boxing
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
}
}
FCVT_S_LU { // 64bit unsigned int to to fp
encoding: 7'b1101000 :: 5'b00011 :: rs1[4:0] :: rm[2:0] :: rd[4:0] :: 7'b1010011;
assembly:"{name(rm)}, f {rd}, {name(rs1)}";
behavior: {
unsigned<32> res = fcvt_64_32(X[rs1 % RFS], 3, rm);
if (FLEN == 32)
F[rd] = res;
else { // NaN boxing
F[rd] = ((signed<64>)-1 << 32) | (unsigned<FLEN>)res;
}
}
}
}
}