Merge pull request #113 from tum-ei-eda/corev-tests

Update Core-V test files

examples/corev_demo.py

@@ -84,7 +84,19 @@
 
 # Load test inputs
 test_files = [
-    EXAMPLES_DIR / "tests" / "xcorev" / "*.inline_asm.c",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "alu" / "*.c",
+    EXAMPLES_DIR / "tests" / "xcorev" / "alu" / "*.s",
+    EXAMPLES_DIR / "tests" / "xcorev" / "alu" / "*.ll",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "mac" / "*.s",
+    EXAMPLES_DIR / "tests" / "xcorev" / "mac" / "*.ll",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "bitmanip" / "*.s",
+    EXAMPLES_DIR / "tests" / "xcorev" / "bitmanip" / "*.ll",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "bi" / "*.s",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "bi" / "*.ll",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "simd" / "*.s",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "simd" / "*.ll",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "mem" / "*.s",
+    # EXAMPLES_DIR / "tests" / "xcorev" / "mem" / "*.ll",
 ]
 seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True)
 

examples/tests/xcorev/alu/cv-abs.test-cg.ll

@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+declare i32 @llvm.abs.i32(i32, i1)
+
+define i32 @abs(i32 %a) {
+; CHECK-LABEL: abs:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.abs a0, a0
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.abs.i32(i32 %a, i1 false)
+  ret i32 %1
+}

examples/tests/xcorev/alu/cv-abs.test-mc-invalid.s

@@ -0,0 +1,14 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcorevalu %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.abs t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.abs t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction

examples/tests/xcorev/alu/cv-abs.test-mc.s

@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.abs t0, t1
+# CHECK-INSTR: seal5.cv.abs t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x50]
+
+seal5.cv.abs a0, a1
+# CHECK-INSTR: seal5.cv.abs a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x50]

examples/tests/xcorev/alu/cv-addn.test-cg.ll

@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+define i32 @addN(i32 %a, i32 %b) {
+; CHECK-LABEL: addN:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.addN a0, a0, a1, 5
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = ashr i32 %1, 5
+  ret i32 %2
+}

examples/tests/xcorev/alu/cv-addn.test-mc-invalid.s

@@ -0,0 +1,26 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcorevalu %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+seal5.cv.addN t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+seal5.cv.addN t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+seal5.cv.addN t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+seal5.cv.addN t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addN t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addN 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addN t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+seal5.cv.addN t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction

examples/tests/xcorev/alu/cv-addn.test-mc.s

@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.addN t0, t1, t2, 0
+# CHECK-INSTR: seal5.cv.addN t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x00]
+
+seal5.cv.addN t0, t1, t2, 16
+# CHECK-INSTR: seal5.cv.addN t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x20]
+
+seal5.cv.addN a0, a1, zero, 31
+# CHECK-INSTR: seal5.cv.addN a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0x3e]

examples/tests/xcorev/alu/cv-addnr.test-cg.ll

@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+define i32 @addNr(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: addNr:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.addNr a0, a1, a2
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = ashr i32 %1, %c
+  ret i32 %2
+}

examples/tests/xcorev/alu/cv-addnr.test-mc-invalid.s

@@ -0,0 +1,17 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcorevalu %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+seal5.cv.addNr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addNr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addNr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addNr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+seal5.cv.addNr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction

examples/tests/xcorev/alu/cv-addnr.test-mc.s

@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.addNr t0, t1, t2
+# CHECK-INSTR: seal5.cv.addNr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x80]
+
+seal5.cv.addNr a0, a1, a2
+# CHECK-INSTR: seal5.cv.addNr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x80]

examples/tests/xcorev/alu/cv-addrn.test-cg.ll

@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+define i32 @addRN(i32 %a, i32 %b) {
+; CHECK-LABEL: addRN:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.addRN a0, a0, a1, 5
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = add i32 %1, 16
+  %3 = ashr i32 %2, 5
+  ret i32 %3
+}

examples/tests/xcorev/alu/cv-addrn.test-mc-invalid.s

@@ -0,0 +1,26 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcorevalu %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+seal5.cv.addRN t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+seal5.cv.addRN t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+seal5.cv.addRN t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+seal5.cv.addRN t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addRN t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addRN 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addRN t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+seal5.cv.addRN t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction

examples/tests/xcorev/alu/cv-addrn.test-mc.s

@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.addRN t0, t1, t2, 0
+# CHECK-INSTR: seal5.cv.addRN t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x80]
+
+seal5.cv.addRN t0, t1, t2, 16
+# CHECK-INSTR: seal5.cv.addRN t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xa0]
+
+seal5.cv.addRN a0, a1, zero, 31
+# CHECK-INSTR: seal5.cv.addRN a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0xbe]

examples/tests/xcorev/alu/cv-addrnr.test-cg.ll

@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+define i32 @addRNr(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: addRNr:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.addRNr a0, a1, a2
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = shl i32 1, %c
+  %3 = lshr i32 %2, 1
+  %4 = add i32 %1, %3
+  %5 = ashr i32 %4, %c
+  ret i32 %5
+}

examples/tests/xcorev/alu/cv-addrnr.test-mc-invalid.s

@@ -0,0 +1,17 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcorevalu %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+seal5.cv.addRNr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addRNr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addRNr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+seal5.cv.addRNr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+seal5.cv.addRNr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction

examples/tests/xcorev/alu/cv-addrnr.test-mc.s

@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.addRNr t0, t1, t2
+# CHECK-INSTR: seal5.cv.addRNr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x84]
+
+seal5.cv.addRNr a0, a1, a2
+# CHECK-INSTR: seal5.cv.addRNr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x84]

examples/tests/xcorev/alu/cv-addun.test-cg.ll

@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+define i32 @adduN(i32 %a, i32 %b) {
+; CHECK-LABEL: adduN:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.adduN a0, a0, a1, 5
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = lshr i32 %1, 5
+  ret i32 %2
+}

examples/tests/xcorev/alu/cv-addun.test-mc.s

@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.adduN t0, t1, t2, 0
+# CHECK-INSTR: seal5.cv.adduN t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x40]
+
+seal5.cv.adduN t0, t1, t2, 16
+# CHECK-INSTR: seal5.cv.adduN t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x60]
+
+seal5.cv.adduN a0, a1, zero, 31
+# CHECK-INSTR: seal5.cv.adduN a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0x7e]

examples/tests/xcorev/alu/cv-addunr.test-cg.ll

@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+define i32 @adduNr(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: adduNr:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.adduNr a0, a1, a2
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = lshr i32 %1, %c
+  ret i32 %2
+}

examples/tests/xcorev/alu/cv-addunr.test-mc.s

@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.adduNr t0, t1, t2
+# CHECK-INSTR: seal5.cv.adduNr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x82]
+
+seal5.cv.adduNr a0, a1, a2
+# CHECK-INSTR: seal5.cv.adduNr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x82]

examples/tests/xcorev/alu/cv-addurn.test-cg.ll

@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+define i32 @adduRN(i32 %a, i32 %b) {
+; CHECK-LABEL: adduRN:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.adduRN a0, a0, a1, 5
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = add i32 %1, 16
+  %3 = lshr i32 %2, 5
+  ret i32 %3
+}

examples/tests/xcorev/alu/cv-addurn.test-mc.s

@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.adduRN t0, t1, t2, 0
+# CHECK-INSTR: seal5.cv.adduRN t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xc0]
+
+seal5.cv.adduRN t0, t1, t2, 16
+# CHECK-INSTR: seal5.cv.adduRN t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xe0]
+
+seal5.cv.adduRN a0, a1, zero, 31
+# CHECK-INSTR: seal5.cv.adduRN a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0xfe]

examples/tests/xcorev/alu/cv-addurnr.test-cg.ll

@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+define i32 @adduRNr(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: adduRNr:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.adduRNr a0, a1, a2
+; CHECK-NEXT:    ret
+  %1 = add i32 %a, %b
+  %2 = shl i32 1, %c
+  %3 = lshr i32 %2, 1
+  %4 = add i32 %1, %3
+  %5 = lshr i32 %4, %c
+  ret i32 %5
+}

examples/tests/xcorev/alu/cv-addurnr.test-mc.s

@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+seal5.cv.adduRNr t0, t1, t2
+# CHECK-INSTR: seal5.cv.adduRNr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x86]
+
+seal5.cv.adduRNr a0, a1, a2
+# CHECK-INSTR: seal5.cv.adduRNr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x86]

examples/tests/xcorev/alu/cv-clip.test-cg.ll

@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+m,+xcorevalu -verify-machineinstrs -global-isel=1 < %s \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL
+
+declare i32 @llvm.smin.i32(i32, i32)
+declare i32 @llvm.smax.i32(i32, i32)
+
+define i32 @clip(i32 %a) {
+; CHECK-LABEL: clip:
+; CHECK:       # %bb.0:
+; CHECK-GISEL-NEXT:    seal5.cv.clip a0, a0, 7
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.smax.i32(i32 %a, i32 -64)
+  %2 = call i32 @llvm.smin.i32(i32 %1, i32 63)
+  ret i32 %2
+}