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CPU.c
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CPU.c
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//(c) uARM project https://github.com/uARM-Palm/uARM uARM@dmitry.gr
#include "palmoscalls.h"
#include "gdbstub.h"
#include <string.h>
#include <stdlib.h>
#include "icache.h"
#include "cp15.h"
#include "util.h"
#include "CPU.h"
#include "MMU.h"
#include "mem.h"
#define unlikely(x) __builtin_expect((x), 0)
#define likely(x) __builtin_expect((x), 1)
#define ARM_MODE_2_REG 0x0F
#define ARM_MODE_2_WORD 0x10
#define ARM_MODE_2_LOAD 0x20
#define ARM_MODE_2_T 0x40
#define ARM_MODE_2_INV 0x80
#define ARM_MODE_3_REG 0x0F //flag for actual reg number used
#define ARM_MODE_3_TYPE 0x30 //flag for the below 4 types
#define ARM_MODE_3_H 0x00
#define ARM_MODE_3_SH 0x10
#define ARM_MODE_3_SB 0x20
#define ARM_MODE_3_D 0x30
#define ARM_MODE_3_LOAD 0x40
#define ARM_MODE_3_INV 0x80
#define ARM_MODE_4_REG 0x0F
#define ARM_MODE_4_INC 0x10 //incr or decr
#define ARM_MODE_4_BFR 0x20 //before or after
#define ARM_MODE_4_WBK 0x40 //writeback?
#define ARM_MODE_4_S 0x80 //S bit set?
#define ARM_MODE_5_REG 0x0F
#define ARM_MODE_5_IS_OPTION 0x10 //is value option (as opposed to offset)
#define ARM_MODE_5_RR 0x20 //MCRR or MRCC instrs
#define REG_NO_SP 13
#define REG_NO_LR 14
#define REG_NO_PC 15
/*
coprocessors:
0 - DSP (pxa only)
0, 1 - WMMX (pxa only)
11 - VFP (arm standard)
15 - system control (arm standard)
*/
struct ArmBankedRegs{
uint32_t R13, R14;
uint32_t SPSR; //usr mode doesn't have an SPSR
};
struct ArmCpu {
uint32_t regs[16]; //current active regs as per current mode
uint32_t SPSR;
bool N, Z, C, V, Q, T, I, F;
uint8_t M;
uint32_t curInstrPC;
struct ArmBankedRegs bank_usr; //usr regs when in another mode
struct ArmBankedRegs bank_svc; //svc regs when in another mode
struct ArmBankedRegs bank_abt; //abt regs when in another mode
struct ArmBankedRegs bank_und; //und regs when in another mode
struct ArmBankedRegs bank_irq; //irq regs when in another mode
struct ArmBankedRegs bank_fiq; //fiq regs when in another mode
uint32_t extra_regs[5]; //fiq regs when not in fiq mode, usr regs when in fiq mode. R8-12
uint16_t waitingIrqs;
uint16_t waitingFiqs;
uint16_t CPAR;
struct ArmCoprocessor coproc[16]; //coprocessors
// various other cpu config options
uint32_t vectorBase; //address of vector base
uint32_t pid; //for fcse
struct icache *ic;
struct ArmMmu *mmu;
struct ArmMem *mem;
struct ArmCP15 *cp15;
struct stub *debugStub;
};
static uint32_t cpuPrvClz(uint32_t val)
{
if (!val)
return 32;
if (sizeof(int) == sizeof(uint32_t))
return __builtin_clz(val);
if (sizeof(long) == sizeof(uint32_t))
return __builtin_clzl(val);
if (sizeof(long long) == sizeof(uint32_t))
return __builtin_clzll(val);
ERR("CLZ undefined");
}
static uint32_t cpuPrvROR(uint32_t val, uint_fast8_t ror)
{
if (ror)
val = (val >> ror) | (val << (32 - ror));
return val;
}
static void cpuPrvSetPC(struct ArmCpu *cpu, uint32_t pc) //with interworking
{
cpu->regs[REG_NO_PC] = pc &~ 1UL;
cpu->T = (pc & 1);
if (!cpu->T && (pc & 2))
ERR("Attempt to branch to non-word-aligned ARM address");
}
static uint32_t cpuPrvGetRegNotPC(struct ArmCpu *cpu, uint_fast8_t reg, bool wasT, bool specialPC)
{
return cpu->regs[reg];
}
static uint32_t cpuPrvGetReg(struct ArmCpu *cpu, uint_fast8_t reg, bool wasT, bool specialPC)
{
uint32_t ret;
ret = cpu->regs[reg];
if (reg == REG_NO_PC) {
ret += wasT ? 2 : 4;
if (wasT && specialPC)
ret &=~ 3UL;
}
return ret;
}
static void cpuPrvSetRegNotPC(struct ArmCpu *cpu, uint_fast8_t reg, uint32_t val)
{
cpu->regs[reg] = val;
}
static void cpuPrvSetReg(struct ArmCpu *cpu, uint_fast8_t reg, uint32_t val)
{
if (reg == REG_NO_PC)
cpuPrvSetPC(cpu, val);
else
cpuPrvSetRegNotPC(cpu, reg, val);
}
static struct ArmBankedRegs* cpuPrvModeToBankedRegsPtr(struct ArmCpu *cpu, uint_fast8_t mode)
{
switch (mode) {
case ARM_SR_MODE_USR:
case ARM_SR_MODE_SYS:
return &cpu->bank_usr;
case ARM_SR_MODE_FIQ:
return &cpu->bank_fiq;
case ARM_SR_MODE_IRQ:
return &cpu->bank_irq;
case ARM_SR_MODE_SVC:
return &cpu->bank_svc;
case ARM_SR_MODE_ABT:
return &cpu->bank_abt;
case ARM_SR_MODE_UND:
return &cpu->bank_und;
default:
ERR("Invalid mode passed to cpuPrvModeToBankedRegsPtr()");
return NULL;
}
}
static void cpuPrvSwitchToMode(struct ArmCpu *cpu, uint_fast8_t newMode)
{
struct ArmBankedRegs *saveTo, *getFrom;
uint_fast8_t i, curMode;
uint32_t tmp;
curMode = cpu->M;
if (curMode == newMode)
return;
if (curMode == ARM_SR_MODE_FIQ || newMode == ARM_SR_MODE_FIQ) { //bank/unbank the fiq regs
for (i = 0; i < 5; i++) {
tmp = cpu->extra_regs[i];
cpu->extra_regs[i] = cpu->regs[i + 8];
cpu->regs[i + 8] = tmp;
}
}
saveTo = cpuPrvModeToBankedRegsPtr(cpu, curMode);
getFrom = cpuPrvModeToBankedRegsPtr(cpu, newMode);
if (saveTo == getFrom)
return; //we're done if no regs to switch [this happens if we switch user<->system]
saveTo->R13 = cpu->regs[REG_NO_SP];
saveTo->R14 = cpu->regs[REG_NO_LR];
saveTo->SPSR = cpu->SPSR;
cpu->regs[REG_NO_SP] = getFrom->R13;
cpu->regs[REG_NO_LR] = getFrom->R14;
cpu->SPSR = getFrom->SPSR;
cpu->M = newMode;
}
static void cpuPrvSetPSRlo8(struct ArmCpu *cpu, uint_fast8_t val)
{
cpuPrvSwitchToMode(cpu, val & ARM_SR_M);
cpu->T = !!(val & ARM_SR_T);
cpu->F = !!(val & ARM_SR_F);
cpu->I = !!(val & ARM_SR_I);
}
static void cpuPrvSetPSRhi8(struct ArmCpu *cpu, uint32_t val)
{
cpu->N = !!(val & ARM_SR_N);
cpu->Z = !!(val & ARM_SR_Z);
cpu->C = !!(val & ARM_SR_C);
cpu->V = !!(val & ARM_SR_V);
cpu->Q = !!(val & ARM_SR_Q);
}
static uint32_t cpuPrvMaterializeCPSR(struct ArmCpu *cpu)
{
uint32_t ret = 0;
if (cpu->N)
ret |= ARM_SR_N;
if (cpu->Z)
ret |= ARM_SR_Z;
if (cpu->C)
ret |= ARM_SR_C;
if (cpu->V)
ret |= ARM_SR_V;
if (cpu->Q)
ret |= ARM_SR_Q;
if (cpu->T)
ret |= ARM_SR_T;
if (cpu->I)
ret |= ARM_SR_I;
if (cpu->F)
ret |= ARM_SR_F;
ret |= cpu->M;
return ret;
}
uint32_t cpuGetRegExternal(struct ArmCpu *cpu, uint_fast8_t reg)
{
if (reg < 16) // real reg
return (reg == REG_NO_PC) ? (cpu->curInstrPC + (cpu->T ? 1 : 0)) : cpu->regs[reg];
else if (reg == ARM_REG_NUM_CPSR)
return cpuPrvMaterializeCPSR(cpu);
else if (reg == ARM_REG_NUM_SPSR)
return cpu->SPSR;
else
return 0;
}
void cpuSetReg(struct ArmCpu *cpu, uint_fast8_t reg, uint32_t val)
{
if (reg == ARM_REG_NUM_CPSR) {
cpuPrvSetPSRlo8(cpu, val);
cpuPrvSetPSRhi8(cpu, val);
}
else if (reg < 16)
cpuPrvSetReg(cpu, reg, val);
}
#define cpuSetReg _DO_NOT_USE_cpuSetReg_IN_CPU_C_
static void cpuPrvException(struct ArmCpu *cpu, uint32_t vector_pc, uint32_t lr, uint_fast8_t newLowBits) //enters arm mode
{
uint32_t spsr = cpuPrvMaterializeCPSR(cpu);
cpuPrvSetPSRlo8(cpu, newLowBits);
cpu->SPSR = spsr;
cpu->regs[REG_NO_LR] = lr;
cpu->regs[REG_NO_PC] = vector_pc;
}
//input addr is VA not MVA
static void cpuPrvHandleMemErr(struct ArmCpu *cpu, uint32_t addr, uint_fast8_t sz, bool write, bool instrFetch, uint_fast8_t fsr)
{
//fprintf(stderr, "access error to 0x%08x with fsr %u from 0x%08x\n", addr, fsr, cpu->regs[REG_NO_PC]);
//FCSE
if (addr < 0x02000000UL) //report addr is MVA
addr |= cpu->pid;
cp15SetFaultStatus(cpu->cp15, addr, fsr);
if (instrFetch) {
//handle prefetch abort (LR is addr of aborted instr + 4)
cpuPrvException(cpu, cpu->vectorBase + ARM_VECTOR_OFFT_P_ABT, cpu->curInstrPC + 4, ARM_SR_MODE_ABT | ARM_SR_I);
}
else {
//handle data abort (LR is addr of aborted instr + 8)
cpuPrvException(cpu, cpu->vectorBase + ARM_VECTOR_OFFT_D_ABT, cpu->curInstrPC + 8, ARM_SR_MODE_ABT | ARM_SR_I);
}
}
static uint32_t cpuPrvArmAdrMode_1(struct ArmCpu *cpu, uint32_t instr, bool* carryOutP, bool wasT, bool specialPC)
{
uint_fast8_t v, a;
bool co = cpu->C; //be default carry out = C flag
uint32_t ret;
if (instr & 0x02000000UL) { //immed
v = (instr >> 7) & 0x1E;
ret = cpuPrvROR(instr & 0xFF, v);
if (v)
co = !!(ret & 0x80000000UL);
}
else {
v = (instr >> 5) & 3; //get shift type
ret = cpuPrvGetReg(cpu, instr & 0x0F, wasT, specialPC); //get Rm
if (instr & 0x00000010UL) { //reg with reg shift
a = cpuPrvGetRegNotPC(cpu, (instr >> 8) & 0x0F, wasT, specialPC); //get the relevant part of Rs, we only care for lower 8 bits (note we use uint8 for this)
if (a != 0) { //else all is already good
switch (v) { //perform shifts
case 0: //LSL
if (a < 32) {
co = (ret >> (32 - a)) & 1;
ret = ret << a;
}
else if (a == 32) {
co = ret & 1;
ret = 0;
}
else { // >32
co = 0;
ret = 0;
}
break;
case 1: //LSR
if (a < 32) {
co = (ret >> (a - 1)) & 1;
ret = ret >> a;
}
else if (a == 32) {
co = ret >> 31;
ret = 0;
}
else { // >32
co = 0;
ret = 0;
}
break;
case 2: //ASR
if (a < 32) {
co = (ret >> (a - 1)) & 1;
ret = ((int32_t)ret >> a);
}
else { // >=32
if (ret & 0x80000000UL) {
co = 1;
ret = 0xFFFFFFFFUL;
}
else {
co = 0;
ret = 0;
}
}
break;
case 3: //ROR
if (a == 0) {
//nothing...
}
else {
a &= 0x1F;
if (a == 0)
co = ret >> 31;
else {
co = (ret >> (a - 1)) & 1;
ret = cpuPrvROR(ret, a);
}
}
break;
}
}
}
else { //reg with immed shift
a = (instr >> 7) & 0x1F; //get imm
switch (v) {
case 0: //LSL
if (a == 0) {
//nothing
}
else {
co = (ret >> (32 - a)) & 1;
ret = ret << a;
}
break;
case 1: //LSR
if (a == 0) {
co = ret >> 31;
ret = 0;
}
else {
co = (ret >> (a - 1)) & 1;
ret = ret >> a;
}
break;
case 2: //ASR
if (a == 0) {
if (ret & 0x80000000UL) {
co = 1;
ret = 0xFFFFFFFFUL;
}
else {
co = 0;
ret = 0;
}
}
else {
co = (ret >> (a - 1)) & 1;
if (ret & 0x80000000UL)
ret = (ret >> a) | (0xFFFFFFFFUL << (32 - a));
else
ret = ret >> a;
}
break;
case 3: //ROR or RRX
if (a == 0) { //RRX
a = co;
co = ret & 1;
ret = ret >> 1;
if (a)
ret |= 0x80000000UL;
}
else {
co = (ret >> (a - 1)) & 1;
ret = cpuPrvROR(ret, a);
}
break;
}
}
}
*carryOutP = co;
return ret;
}
/*
idea:
addbefore is what to add to add to base reg before addressing, addafter is what to add after. we ALWAYS do writeback, but if not requested by instr, it will be zero
for [Rx, 5] baseReg = x addbefore = 5 addafter = -5
for [Rx, 5]! baseReg = x addBefore = 0 addafter = 0
for [Rx], 5 baseReg = x addBefore = 0 addAfter = 5
t = T bit (LDR vs LDRT)
baseReg is returned in return val along with flags:
ARM_MODE_2_REG is mask for reg
ARM_MODE_2_WORD is flag for word access
ARM_MODE_2_LOAD is flag for load
ARM_MODE_2_INV is flag for invalid instructions
ARM_MODE_2_T is flag for T
*/
static uint_fast8_t cpuPrvArmAdrMode_2(struct ArmCpu *cpu, uint32_t instr, uint32_t* addBeforeP, uint32_t* addWritebackP, bool wasT, bool specialPC)
{
uint_fast8_t reg, shift;
uint32_t val;
reg = (instr >> 16) & 0x0F;
if (!(instr & 0x02000000UL)) //immediate
val = instr & 0xFFFUL;
else { //[scaled] register
if (instr & 0x00000010UL)
reg |= ARM_MODE_2_INV; //invalid instrucitons need to be reported
val = cpuPrvGetRegNotPC(cpu, instr & 0x0F, wasT, specialPC);
shift = (instr >> 7) & 0x1F;
switch ((instr >> 5) & 3) {
case 0: //LSL
val <<= shift;
break;
case 1: //LSR
val = shift ? (val >> shift) : 0;
break;
case 2: //ASR
val = shift ? (uint32_t)((((int32_t)val) >> shift)) : ((val & 0x80000000UL) ? 0xFFFFFFFFUL : 0x00000000UL);
break;
case 3: //ROR/RRX
if (shift)
val = cpuPrvROR(val, shift);
else { //RRX
val = val >> 1;
if (cpu->C)
val |= 0x80000000UL;
}
}
}
if (!(instr & 0x00400000UL))
reg |= ARM_MODE_2_WORD;
if (instr & 0x00100000UL)
reg |= ARM_MODE_2_LOAD;
if (!(instr & 0x00800000UL))
val = -val;
if (!(instr & 0x01000000UL)) {
*addBeforeP = 0;
*addWritebackP = val;
if (instr & 0x00200000UL)
reg |= ARM_MODE_2_T;
}
else if (instr & 0x00200000UL) {
*addBeforeP = val;
*addWritebackP = val;
}
else {
*addBeforeP = val;
*addWritebackP = 0;
}
return reg;
}
/*
same comments as for addr mode 2 apply
#define ARM_MODE_3_REG 0x0F //flag for actual reg number used
#define ARM_MODE_3_TYPE 0x30 //flag for the below 4 types
#define ARM_MODE_3_H 0x00
#define ARM_MODE_3_SH 0x10
#define ARM_MODE_3_SB 0x20
#define ARM_MODE_3_D 0x30
#define ARM_MODE_3_LOAD 0x40
#define ARM_MODE_3_INV 0x80
*/
static uint_fast8_t cpuPrvArmAdrMode_3(struct ArmCpu *cpu, uint32_t instr, uint32_t* addBeforeP, uint32_t* addWritebackP, bool wasT, bool specialPC)
{
uint_fast8_t reg;
uint32_t val;
bool S, H, L;
reg = (instr >> 16) & 0x0F;
if (instr & 0x00400000UL) //immediate
val = ((instr >> 4) & 0xF0) | (instr & 0x0F);
else {
if (instr & 0x00000F00UL)
reg |= ARM_MODE_3_INV; //bits 8-11 must be 1 always
val = cpuPrvGetRegNotPC(cpu, instr & 0x0F, wasT, specialPC);
}
L = !!(instr & 0x00100000UL);
H = !!(instr & 0x00000020UL);
S = !!(instr & 0x00000040UL);
if (S && H)
reg |= ARM_MODE_3_SH;
else if (S)
reg |= ARM_MODE_3_SB;
else if (H)
reg |= ARM_MODE_3_H;
else
reg |= ARM_MODE_3_INV; //S == 0 && H == 0 is invalid mode 3 operation
if ((instr & 0x00000090UL) != 0x00000090UL)
reg |= ARM_MODE_3_INV; //bits 4 and 7 must be 1 always
if (S && !L) { //LDRD/STRD is encoded thusly
reg = (reg &~ ARM_MODE_3_TYPE) | ARM_MODE_3_D;
L = !H;
}
if (L)
reg |= ARM_MODE_3_LOAD;
if (!(instr & 0x00800000UL))
val = -val;
if (!(instr & 0x01000000UL)) {
*addBeforeP = 0;
*addWritebackP = val;
if (instr & 0x00200000UL)
reg |= ARM_MODE_3_INV; //W must be 0 in this case, else unpredictable (in this case - invalid instr)
}
else if (instr & 0x00200000UL) {
*addBeforeP = val;
*addWritebackP = val;
}
else {
*addBeforeP = val;
*addWritebackP = 0;
}
return reg;
}
/*
#define ARM_MODE_4_REG 0x0F
#define ARM_MODE_4_INC 0x10 //incr or decr
#define ARM_MODE_4_BFR 0x20 //after or before
#define ARM_MODE_4_WBK 0x40 //writeback?
#define ARM_MODE_4_S 0x80 //S bit set?
*/
static uint_fast8_t cpuPrvArmAdrMode_4(struct ArmCpu *cpu, uint32_t instr, bool usesUsrRegs, uint_fast16_t* regs)
{
uint_fast8_t reg;
*regs = instr & 0xffff;
reg = (instr >> 16) & 0x0F;
if ((instr & 0x00400000UL) && !usesUsrRegs) //real hw ignores "S" in modes that use user mode regs
reg |= ARM_MODE_4_S;
if (instr & 0x00200000UL)
reg |= ARM_MODE_4_WBK;
if (instr & 0x00800000UL)
reg |= ARM_MODE_4_INC;
if (instr & 0x01000000UL)
reg |= ARM_MODE_4_BFR;
return reg;
}
/*
#define ARM_MODE_5_REG 0x0F
#define ARM_MODE_5_IS_OPTION 0x10 //is value option (as opposed to offset)
#define ARM_MODE_5_RR 0x20 //MCRR or MRCC instrs
*/
static uint_fast8_t cpuPrvArmAdrMode_5(struct ArmCpu *cpu, uint32_t instr, uint32_t* addBeforeP, uint32_t* addAfterP, uint8_t *optionValP)
{
uint_fast8_t reg;
uint32_t val;
val = instr & 0xFF;
reg = (instr >> 16) & 0x0F;
*addBeforeP = 0;
*addAfterP = 0;
*optionValP = 0;
if (!(instr & 0x01000000UL)) { //unindexed or postindexed
if (instr & 0x00200000UL) //postindexed
*addAfterP = val;
else { //unindexed
if (!(instr & 0x00800000UL))
reg |= ARM_MODE_5_RR; //U must be 1 for unindexed, else it is MCRR/MRCC
*optionValP = val;
}
}
else { //offset or preindexed
*addBeforeP = val;
if (instr & 0x00200000UL) //preindexed
*addAfterP = val;
}
if (!(reg & ARM_MODE_5_IS_OPTION)) {
if (!(instr & 0x00800000UL)) {
*addBeforeP = -*addBeforeP;
*addAfterP = -*addAfterP;
}
}
return reg;
}
static void cpuPrvSetPSR(struct ArmCpu *cpu, uint_fast8_t mask, bool privileged, bool R, uint32_t val)
{
if (R) //setting SPSR in sys or usr mode is no harm since they arent used, so just do it without any checks
cpu->SPSR = val;
else {
if (privileged && (mask & 1))
cpuPrvSetPSRlo8(cpu, val);
if (mask & 8)
cpuPrvSetPSRhi8(cpu, val);
}
}
static bool cpuPrvSignedAdditionOverflows(int32_t a, int32_t b, int32_t sum)
{
int32_t c;
return __builtin_add_overflow_i32(a, b, &c);
}
static bool cpuPrvSignedSubtractionOverflows(int32_t a, int32_t b, int32_t diff) //diff = a - b
{
int32_t c;
return __builtin_sub_overflow_i32(a, b, &c);
}
static int32_t cpuPrvMedia_signedSaturate32(int32_t sign)
{
return (sign < 0) ? -0x80000000UL : 0x7ffffffful;
}
static bool cpuPrvMemOpEx(struct ArmCpu *cpu, void* buf, uint32_t vaddr, uint_fast8_t size, bool write, bool priviledged, uint_fast8_t* fsrP, uint_fast8_t memAccessFlags)
{
uint32_t pa;
gdbStubReportMemAccess(cpu->debugStub, vaddr, size, write);
if (size & (size - 1)) { //size is not a power of two
if (fsrP)
*fsrP = 1; //alignment fault;
return false;
}
if (vaddr & (size - 1)) { //bad alignment
if (fsrP)
*fsrP = 1; //alignment fault;
return false;
}
//FCSE
if (vaddr < 0x02000000UL)
vaddr |= cpu->pid;
if (!mmuTranslate(cpu->mmu, vaddr, priviledged, write, &pa, fsrP, NULL))
return false;
if (!memAccess(cpu->mem, pa, size, memAccessFlags | (write ? MEM_ACCESS_TYPE_WRITE : MEM_ACCESS_TYPE_READ), buf)) {
if (fsrP)
*fsrP = 10; //external abort on non-linefetch
return false;
}
return true;
}
//for internal use
static bool cpuPrvMemOp(struct ArmCpu *cpu, void* buf, uint32_t vaddr, uint_fast8_t size, bool write, bool priviledged, uint_fast8_t* fsrP)
{
if (cpuPrvMemOpEx(cpu, buf, vaddr, size, write, priviledged, fsrP, 0))
return true;
// fprintf(stderr, "%c of %u bytes to 0x%08lx failed!\n", (int)(write ? 'W' : 'R'), (unsigned)size, (unsigned long)vaddr);
// gdbStubDebugBreakRequested(cpu->debugStub);
return false;
}
//for external use
bool cpuMemOpExternal(struct ArmCpu *cpu, void* buf, uint32_t vaddr, uint_fast8_t size, bool write) //for external use
{
return cpuPrvMemOpEx(cpu, buf, vaddr, size, write, true, NULL, MEM_ACCCESS_FLAG_NOERROR);
}
#ifdef SUPPORT_AXIM_PRINTF
static uint32_t cpuPrvAximSysPrintfGetParam(struct ArmCpu *cpu, uint32_t *atP)
{
uint32_t at = *atP;
*atP += 4;
return cpuPrvMemOp(cpu, &at, at, 4, false, true, NULL) ? at : 0;
}
static void cpuPrvAximSysPrintf(struct ArmCpu *cpu)
{
if (cpu->curInstrPC == 0x8006EE64UL)
{
uint32_t a = cpu->regs[0] / 2, params = cpu->regs[1], ptr;
bool infmt = false;
uint16_t v;
while (cpuPrvMemOp(cpu, &v, a++ * 2, 2, false, true, NULL) && v) {
if (infmt) switch (v) {
case '%':
fprintf(stderr, "%%");
infmt = false;
break;
case 'a':
fprintf(stderr, "0x%08x", cpuPrvAximSysPrintfGetParam(cpu, ¶ms));
infmt = false;
break;
case '0' ... '9':
case 'l':
case '.':
break;
case 'd':
fprintf(stderr, "%d", cpuPrvAximSysPrintfGetParam(cpu, ¶ms));
infmt = false;
break;
case 'u':
fprintf(stderr, "%u", cpuPrvAximSysPrintfGetParam(cpu, ¶ms));
infmt = false;
break;
case 'x':
case 'X':
fprintf(stderr, "%x", cpuPrvAximSysPrintfGetParam(cpu, ¶ms));
infmt = false;
break;
case 's':
ptr = cpuPrvAximSysPrintfGetParam(cpu, ¶ms) / 2;
while (cpuPrvMemOp(cpu, &v, ptr++ * 2, 2, false, true, NULL) && v)
fprintf(stderr, "%c", v);
infmt = false;
break;
default:
fprintf(stderr, "unknown format modifier %%%c", v);
infmt = false;
break;
}
else if (v == '%')
infmt = true;
else
fprintf(stderr, "%c", v);
}
}
}
#endif
static uint64_t cpuPrv64FromHalves(uint64_t hi, uint32_t lo)
{
//better than shifting in almost all compilers
union {
struct {
#if __BYTE_ORDER == __LITTLE_ENDIAN
uint32_t lo;
uint32_t hi;
#elif __BYTE_ORDER == __BIG_ENDIAN
uint32_t hi;
uint32_t lo;
#else
#error "endianness undefined"
#endif
};
uint64_t val;
} t;
t.hi = hi;
t.lo = lo;
return t.val;
}
static bool cpuPrvSignedSubtractionWithPossibleCarryOverflows(uint32_t a, uint32_t b, uint32_t diff) //diff = a - b
{
return ((a ^ b) & (a ^ diff)) >> 31;
}
static bool cpuPrvSignedAdditionWithPossibleCarryOverflows(uint32_t a, uint32_t b, uint32_t sum)
{
return ((a ^ b ^ 0x80000000UL) & (a ^ sum)) >> 31;
}
#ifdef SUPPORT_Z72_PRINTF
static uint32_t cpuPrvZ72sysPrintfGetParam(struct ArmCpu *cpu, uint32_t *paramIdxP)
{
uint32_t idx = (*paramIdxP)++, val;
if (idx < 4)
return cpu->regs[idx];
idx -= 4;
cpuPrvMemOp(cpu, &val, cpu->regs[REG_NO_SP] + idx * 4, 4, false, true, NULL);
return val;
}
static void cpuPrvZ72sysPrintf(struct ArmCpu *cpu)
{
if (cpu->curInstrPC == 0x200959BCUL)
{
uint32_t a = cpu->regs[0], paramIdx = 1, ptr;
bool infmt = false;
char v;
while (cpuPrvMemOp(cpu, &v, a++, 1, false, true, NULL) && v) {
if (infmt) switch (v) {
case '%':
fprintf(stderr, "%%");
infmt = false;
break;
case 'a':
fprintf(stderr, "0x%08x", cpuPrvZ72sysPrintfGetParam(cpu, ¶mIdx));
infmt = false;
break;
case '0' ... '9':
case 'l':
case '.':
break;
case 'd':
fprintf(stderr, "%d", cpuPrvZ72sysPrintfGetParam(cpu, ¶mIdx));
infmt = false;
break;
case 'u':
fprintf(stderr, "%u", cpuPrvZ72sysPrintfGetParam(cpu, ¶mIdx));
infmt = false;
break;
case 'x':
case 'X':
fprintf(stderr, "%x", cpuPrvZ72sysPrintfGetParam(cpu, ¶mIdx));
infmt = false;
break;
case 's':
ptr = cpuPrvZ72sysPrintfGetParam(cpu, ¶mIdx);
while (cpuPrvMemOp(cpu, &v, ptr++, 1, false, true, NULL) && v)
fprintf(stderr, "%c", v);
infmt = false;