Skip to content

Commit

Permalink
elf2flt: add RISC-V 32-bit support
Browse files Browse the repository at this point in the history
Allow elf2flt to work with RISC-V 32-bit targets. With these changes, the
uclibc toolchain and busybox can work fine for rv32 no MMU systems with
no noticable problem.

Signed-off-by: Charles Lohr <lohr85@gmail.com>
[Rebased onto latest tree for upstreaming]
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Add more ELF relco types and edit commit message]
Signed-off-by: Yimin Gu <ustcymgu@gmail.com>
  • Loading branch information
regymm authored and vapier committed Dec 22, 2023
1 parent 679c94a commit 44e34cb
Show file tree
Hide file tree
Showing 2 changed files with 5 additions and 3 deletions.
6 changes: 4 additions & 2 deletions elf2flt.c
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,7 @@ const char *elf2flt_progname;
#include <elf/v850.h>
#elif defined(TARGET_xtensa)
#include <elf/xtensa.h>
#elif defined(TARGET_riscv64)
#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
#include <elf/riscv.h>
#endif

Expand Down Expand Up @@ -127,6 +127,8 @@ const char *elf2flt_progname;
#define ARCH "xtensa"
#elif defined(TARGET_riscv64)
#define ARCH "riscv64"
#elif defined(TARGET_riscv32)
#define ARCH "riscv32"
#else
#error "Don't know how to support your CPU architecture??"
#endif
Expand Down Expand Up @@ -822,7 +824,7 @@ output_relocs (
goto good_32bit_resolved_reloc_update_text;
default:
goto bad_resolved_reloc;
#elif defined(TARGET_riscv64)
#elif defined(TARGET_riscv64) || defined(TARGET_riscv32)
case R_RISCV_NONE:
case R_RISCV_32_PCREL:
case R_RISCV_ADD8:
Expand Down
2 changes: 1 addition & 1 deletion ld-elf2flt.c
Original file line number Diff line number Diff line change
Expand Up @@ -327,7 +327,7 @@ static int do_final_link(void)
/* riscv adds a global pointer symbol to the linker file with the
"RISCV_GP:" prefix. Remove the prefix for riscv64 architecture and
the entire line for other architectures. */
if (streq(TARGET_CPU, "riscv64"))
if (streq(TARGET_CPU, "riscv64") || streq(TARGET_CPU, "riscv32"))
append_sed(&sed, "^RISCV_GP:", "");
else
append_sed(&sed, "^RISCV_GP:", NULL);
Expand Down

0 comments on commit 44e34cb

Please sign in to comment.