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arduino_8080.ino.z80
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arduino_8080.ino.z80
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//
// Zilog Z80 CPU emulation on an Arduino Nano
// derived from Z80PACK
// Copyright 2024, Udo Munk & Thomas Eberhardt
//
// History:
// 04-MAY-2024 Release 1.0 implements a very basic 8080 system
// 06-MAY-2024 Release 1.1 add support for a ROM in flash
// 07-MAY-2024 Release 1.2 move 8080 memory into a FRAM
// 13-MAY-2024 Release 1.2.1 can run MITS Altair BASIC
// 17-MAY-2024 Release 1.3 switch to code minimized CPU from Thomas Eberhardt
// 18-MAY-2024 Release 1.4 read 8080 code from a file on SD into FRAM
// 20-MAY-2024 Release 1.5.1 added interrupt key and register dump for debugging
// 22-MAY-2024 Release 1.6 boot from a disk image on SD
// 13-JUN-2024 Release 1.6.1 power on jump into boot ROM
//
//#define FRAM_DEBUG 1 // enables FRAM debug messages
//#define DEBUG // enables some application debug messages
#include <stdint.h>
#include <SPI.h>
#include "Adafruit_FRAM_SPI.h"
#include "SdFat.h"
// unused analog pin to seed random generator
#define UAP 7
// chip select pin for FRAM (default)
#define FRAM_CS 10
// chip select pin for SD card
#define SD_CS 9
// interrupt pin, interrupt 0 is already used by the SPI stuff
// so we use interrupt 1 at the D3 pin
#define USERINT 3
// data types for the Z80 CPU
typedef uint8_t BYTE;
typedef int8_t SBYTE;
typedef uint16_t WORD;
// project includes
#include "simcore.h"
#include "memsim.h"
#include "sd-fdc.h"
#include "iosim.h"
#include "config.h"
#if _BYTE_ORDER == _LITTLE_ENDIAN
struct cpu_reg {
union {
struct {
BYTE l;
BYTE h;
};
WORD w;
};
};
#elif _BYTE_ORDER == _BIG_ENDIAN
struct cpu_reg {
union {
struct {
BYTE h;
BYTE l;
};
WORD w;
};
};
#else
#error "Unsupported byte order"
#endif
// Z80 CPU state
struct cpu_state {
struct cpu_reg af; /* primary registers */
struct cpu_reg bc;
struct cpu_reg de;
struct cpu_reg hl;
struct cpu_reg sp; /* stack pointer */
struct cpu_reg pc; /* program counter */
struct cpu_reg af_; /* Z80 alternate registers */
struct cpu_reg bc_;
struct cpu_reg de_;
struct cpu_reg hl_;
struct cpu_reg ix; /* Z80 index registers */
struct cpu_reg iy;
BYTE i; /* Z80 interrupt register */
BYTE r; /* Z80 refresh register (7-bit counter) */
BYTE r_; /* 8th bit of R (can be loaded with LD R,A) */
BYTE iff; /* interupt flags */
} cpu_state;
// other global variables
CPUState State = Running; // CPU state
unsigned long tstates = 0; // executed T-states
// Insure FAT16/FAT32 only
SdFat32 SD;
// Precomputed table for fast sign, zero and parity flag calculation
#define _ 0
#define S S_FLAG
#define Z Z_FLAG
#define P P_FLAG
static const BYTE szp_flags[256] = {
/*00*/ Z|P, _, _, P, _, P, P, _,
/*08*/ _, P, P, _, P, _, _, P,
/*10*/ _, P, P, _, P, _, _, P,
/*18*/ P, _, _, P, _, P, P, _,
/*20*/ _, P, P, _, P, _, _, P,
/*28*/ P, _, _, P, _, P, P, _,
/*30*/ P, _, _, P, _, P, P, _,
/*38*/ _, P, P, _, P, _, _, P,
/*40*/ _, P, P, _, P, _, _, P,
/*48*/ P, _, _, P, _, P, P, _,
/*50*/ P, _, _, P, _, P, P, _,
/*58*/ _, P, P, _, P, _, _, P,
/*60*/ P, _, _, P, _, P, P, _,
/*68*/ _, P, P, _, P, _, _, P,
/*70*/ _, P, P, _, P, _, _, P,
/*78*/ P, _, _, P, _, P, P, _,
/*80*/ S, S|P, S|P, S, S|P, S, S, S|P,
/*88*/ S|P, S, S, S|P, S, S|P, S|P, S,
/*90*/ S|P, S, S, S|P, S, S|P, S|P, S,
/*98*/ S, S|P, S|P, S, S|P, S, S, S|P,
/*a0*/ S|P, S, S, S|P, S, S|P, S|P, S,
/*a8*/ S, S|P, S|P, S, S|P, S, S, S|P,
/*b0*/ S, S|P, S|P, S, S|P, S, S, S|P,
/*b8*/ S|P, S, S, S|P, S, S|P, S|P, S,
/*c0*/ S|P, S, S, S|P, S, S|P, S|P, S,
/*c8*/ S, S|P, S|P, S, S|P, S, S, S|P,
/*d0*/ S, S|P, S|P, S, S|P, S, S, S|P,
/*d8*/ S|P, S, S, S|P, S, S|P, S|P, S,
/*e0*/ S, S|P, S|P, S, S|P, S, S, S|P,
/*e8*/ S|P, S, S, S|P, S, S|P, S|P, S,
/*f0*/ S|P, S, S, S|P, S, S|P, S|P, S,
/*f8*/ S, S|P, S|P, S, S|P, S, S, S|P
};
#undef _
#undef S
#undef Z
#undef P
// This function initializes the CPU into the documented
// state. Prevents assumptions about register contents
// of a just powered CPU, like HL is always 0 in the
// beginning, which is not the case with the silicon.
static void init_cpu(struct cpu_state *cpu_state)
{
cpu_state->pc.w = 0xff00; // normally 0, power on jump to boot ROM
cpu_state->sp.w = random(65535);
cpu_state->af.w = random(65535);
cpu_state->bc.w = random(65535);
cpu_state->de.w = random(65535);
cpu_state->hl.w = random(65535);
cpu_state->af_.w = random(65535);
cpu_state->bc_.w = random(65535);
cpu_state->de_.w = random(65535);
cpu_state->hl_.w = random(65535);
cpu_state->ix.w = random(65535);
cpu_state->iy.w = random(65535);
cpu_state->i = 0;
}
#define FAST_BLOCK
// This function builds the Z80 central processing unit.
// The opcode where PC points to is fetched from the memory
// and PC incremented by one. The opcode is then dispatched
// to execute code, which emulates this Z80 opcode.
//
// For a description of how the arithmetic flags calculation works see:
// http://emulators.com/docs/lazyoverflowdetect_final.pdf
//
// The formula for subtraction carry outs was determined by staring
// intently at some truth tables.
//
// cout contains the carry outs for every bit
void cpu_z80(struct cpu_state *cpu_state)
{
struct cpu_state cpu_regs;
BYTE t, res, cout, P, op, n, curr_ir;
#ifdef FAST_BLOCK
WORD s, d;
int32_t tl; /* loops can run for 65535 * 21 + 16 cycles */
#endif
struct cpu_reg w; /* working register */
struct cpu_reg ir; /* current index register (HL, IX, IY) */
#pragma push_macro("F")
#undef F
#pragma push_macro("SP")
#undef SP
#pragma push_macro("SPH")
#undef SPH
#pragma push_macro("SPL")
#undef SPL
#pragma push_macro("PC")
#undef PC
#define AF cpu_regs.af.w
#define A cpu_regs.af.h
#define F cpu_regs.af.l
#define BC cpu_regs.bc.w
#define B cpu_regs.bc.h
#define C cpu_regs.bc.l
#define DE cpu_regs.de.w
#define D cpu_regs.de.h
#define E cpu_regs.de.l
#define HL cpu_regs.hl.w
#define H cpu_regs.hl.h
#define L cpu_regs.hl.l
#define SP cpu_regs.sp.w
#define SPH cpu_regs.sp.h
#define SPL cpu_regs.sp.l
#define PC cpu_regs.pc.w
#define PCH cpu_regs.pc.h
#define PCL cpu_regs.pc.l
#define AF_ cpu_regs.af_.w
#define BC_ cpu_regs.bc_.w
#define DE_ cpu_regs.de_.w
#define HL_ cpu_regs.hl_.w
#define IX cpu_regs.ix.w
#define IY cpu_regs.iy.w
#define I cpu_regs.i
#define R cpu_regs.r
#define R_ cpu_regs.r_
#define IFF cpu_regs.iff
#define W w.w
#define WH w.h
#define WL w.l
#define IR ir.w
#define IRH ir.h
#define IRL ir.l
#define IR_HL 0 /* values for curr_ir */
#define IR_IX 1
#define IR_IY 2
cpu_regs = *cpu_state;
do {
t = 0;
curr_ir = IR_HL;
IR = HL;
next_opcode:
t += 4;
switch (memrdr(PC++)) { /* execute next opcode */
case 0x00: /* NOP */
case 0x40: /* LD B,B */
case 0x49: /* LD C,C */
case 0x52: /* LD D,D */
case 0x5b: /* LD E,E */
case 0x64: /* LD irh,irh */
case 0x6d: /* LD irl,irl */
case 0x7f: /* LD A,A */
break;
case 0x01: /* LD BC,nn */
C = memrdr(PC++);
B = memrdr(PC++);
t += 6;
break;
case 0x02: /* LD (BC),A */
memwrt(BC, A);
t += 3;
break;
case 0x03: /* INC BC */
BC++;
t += 2;
break;
case 0x04: /* INC B */
P = B;
res = ++B;
finish_inc:
cout = (P & 1) | ((P | 1) & ~res);
F = ((F & C_FLAG) |
((((cout + 64) >> 7) & 1) << P_SHIFT) |
// (((cout >> 3) & 1) << H_SHIFT) |
((cout & 8) << (H_SHIFT - 3)) |
(szp_flags[res] & ~P_FLAG));
/* N_FLAG cleared, C_FLAG unchanged */
break;
case 0x05: /* DEC B */
P = B;
res = --B;
finish_dec:
cout = (~P & 1) | ((~P | 1) & res);
F = ((F & C_FLAG) |
((((cout + 64) >> 7) & 1) << P_SHIFT) |
// (((cout >> 3) & 1) << H_SHIFT) |
((cout & 8) << (H_SHIFT - 3)) |
N_FLAG |
(szp_flags[res] & ~P_FLAG));
/* C_FLAG unchanged */
break;
case 0x06: /* LD B,n */
B = memrdr(PC++);
t += 3;
break;
case 0x07: /* RLCA */
res = ((A & 0x80) >> 7) & 1;
F = (F & ~(H_FLAG | N_FLAG | C_FLAG)) | (res << C_SHIFT);
/* S_FLAG, Z_FLAG, and P_FLAG unchanged */
A = (A << 1) | res;
break;
case 0x08: /* EX AF,AF' */
W = AF;
AF = AF_;
AF_ = W;
break;
case 0x09: /* ADD ir,BC */
W = IR + BC;
cout = (IRH & B) | ((IRH | B) & ~WH);
finish_addir:
F = ((F & ~(H_FLAG | N_FLAG | C_FLAG)) |
(((cout >> 3) & 1) << H_SHIFT) |
(((cout >> 7) & 1) << C_SHIFT));
/* S_FLAG, Z_FLAG, and P_FLAG unchanged */
IR = W;
t += 7;
break;
case 0x0a: /* LD A,(BC) */
A = memrdr(BC);
t += 3;
break;
case 0x0b: /* DEC BC */
BC--;
t += 2;
break;
case 0x0c: /* INC C */
P = C;
res = ++C;
goto finish_inc;
case 0x0d: /* DEC C */
P = C;
res = --C;
goto finish_dec;
case 0x0e: /* LD C,n */
C = memrdr(PC++);
t += 3;
break;
case 0x0f: /* RRCA */
res = A & 1;
F = (F & ~(H_FLAG | N_FLAG | C_FLAG)) | (res << C_SHIFT);
/* S_FLAG, Z_FLAG, and P_FLAG unchanged */
A = (A >> 1) | (res << 7);
break;
case 0x10: /* DJNZ n */
P = memrdr(PC++);
t++;
if (--B) {
PC += (SBYTE) P;
t += 8;
}
break;
case 0x11: /* LD DE,nn */
E = memrdr(PC++);
D = memrdr(PC++);
t += 6;
break;
case 0x12: /* LD (DE),A */
memwrt(DE, A);
t += 3;
break;
case 0x13: /* INC DE */
DE++;
t += 2;
break;
case 0x14: /* INC D */
P = D;
res = ++D;
goto finish_inc;
case 0x15: /* DEC D */
P = D;
res = --D;
goto finish_dec;
case 0x16: /* LD D,n */
D = memrdr(PC++);
t += 3;
break;
case 0x17: /* RLA */
res = (F >> C_SHIFT) & 1;
F = ((F & ~(H_FLAG | N_FLAG | C_FLAG)) |
((((A & 0x80) >> 7) & 1) << C_SHIFT));
/* S_FLAG, Z_FLAG, and P_FLAG unchanged */
A = (A << 1) | res;
break;
case 0x18: /* JR n */
P = memrdr(PC++);
PC += (SBYTE) P;
t += 8;
break;
case 0x19: /* ADD ir,DE */
W = IR + DE;
cout = (IRH & D) | ((IRH | D) & ~WH);
goto finish_addir;
case 0x1a: /* LD A,(DE) */
A = memrdr(DE);
t += 3;
break;
case 0x1b: /* DEC DE */
DE--;
t += 2;
break;
case 0x1c: /* INC E */
P = E;
res = ++E;
goto finish_inc;
case 0x1d: /* DEC E */
P = E;
res = --E;
goto finish_dec;
case 0x1e: /* LD E,n */
E = memrdr(PC++);
t += 3;
break;
case 0x1f: /* RRA */
res = (F >> C_SHIFT) & 1;
F = (F & ~(H_FLAG | N_FLAG | C_FLAG)) | ((A & 1) << C_SHIFT);
/* S_FLAG, Z_FLAG, and P_FLAG unchanged */
A = (A >> 1) | (res << 7);
break;
case 0x20: /* JR NZ,n */
res = !(F & Z_FLAG);
finish_jrc:
P = memrdr(PC++);
t += 3;
if (res) {
PC += (SBYTE) P;
t += 5;
}
break;
case 0x21: /* LD ir,nn */
IRL = memrdr(PC++);
IRH = memrdr(PC++);
t += 6;
break;
case 0x22: /* LD (nn),ir */
WL = memrdr(PC++);
WH = memrdr(PC++);
memwrt(W, IRL);
memwrt(W + 1, IRH);
t += 12;
break;
case 0x23: /* INC ir */
IR++;
t += 2;
break;
case 0x24: /* INC irh */
P = IRH;
res = ++IRH;
goto finish_inc;
case 0x25: /* DEC irh */
P = IRH;
res = --IRH;
goto finish_dec;
case 0x26: /* LD irh,n */
IRH = memrdr(PC++);
t += 3;
break;
case 0x27: /* DAA */
P = 0;
if (((A & 0xf) > 9) || (F & H_FLAG))
P |= 0x06;
if ((A > 0x99) || (F & C_FLAG)) {
F |= C_FLAG;
P |= 0x60;
}
if (F & N_FLAG) {
res = A - P;
cout = (~A & P) | ((~A | P) & res);
} else {
res = A + P;
cout = (A & P) | ((A | P) & ~res);
}
F = ((F & (N_FLAG | C_FLAG)) |
(((cout >> 3) & 1) << H_SHIFT) |
szp_flags[res]);
/* N_FLAG unchanged */
A = res;
break;
case 0x28: /* JR Z,n */
res = F & Z_FLAG;
goto finish_jrc;
case 0x29: /* ADD ir,ir */
W = IR << 1;
cout = IRH | (IRH & ~WH);
goto finish_addir;
case 0x2a: /* LD ir,(nn) */
WL = memrdr(PC++);
WH = memrdr(PC++);
IRL = memrdr(W);
IRH = memrdr(W + 1);
t += 12;
break;
case 0x2b: /* DEC ir */
IR--;
t += 2;
break;
case 0x2c: /* INC irl */
P = IRL;
res = ++IRL;
goto finish_inc;
case 0x2d: /* DEC irl */
P = IRL;
res = --IRL;
goto finish_dec;
case 0x2e: /* LD irl,n */
IRL = memrdr(PC++);
t += 3;
break;
case 0x2f: /* CPL */
A = ~A;
F |= H_FLAG | N_FLAG;
/* S_FLAG, Z_FLAG, P_FLAG, and C_FLAG unchanged */
break;
case 0x30: /* JR NC,n */
res = !(F & C_FLAG);
goto finish_jrc;
case 0x31: /* LD SP,nn */
SPL = memrdr(PC++);
SPH = memrdr(PC++);
t += 6;
break;
case 0x32: /* LD (nn),A */
WL = memrdr(PC++);
WH = memrdr(PC++);
memwrt(W, A);
t += 9;
break;
case 0x33: /* INC SP */
SP++;
t += 2;
break;
case 0x34: /* INC (ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
P = memrdr(W);
res = P + 1;
memwrt(W, res);
t += 7;
goto finish_inc;
case 0x35: /* DEC (ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
P = memrdr(W);
res = P - 1;
memwrt(W, res);
t += 7;
goto finish_dec;
case 0x36: /* LD (ir),n */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 5;
}
memwrt(W, memrdr(PC++));
t += 6;
break;
case 0x37: /* SCF */
F |= C_FLAG;
F &= ~(N_FLAG | H_FLAG);
/* S_FLAG, Z_FLAG, and P_FLAG unchanged */
break;
case 0x38: /* JR C,n */
res = F & C_FLAG;
goto finish_jrc;
case 0x39: /* ADD ir,SP */
W = IR + SP;
cout = (IRH & SPH) | ((IRH | SPH) & ~WH);
goto finish_addir;
case 0x3a: /* LD A,(nn) */
WL = memrdr(PC++);
WH = memrdr(PC++);
A = memrdr(W);
t += 9;
break;
case 0x3b: /* DEC SP */
SP--;
t += 2;
break;
case 0x3c: /* INC A */
P = A;
res = ++A;
goto finish_inc;
case 0x3d: /* DEC A */
P = A;
res = --A;
goto finish_dec;
case 0x3e: /* LD A,n */
A = memrdr(PC++);
t += 3;
break;
case 0x3f: /* CCF */
if (F & C_FLAG) {
F |= H_FLAG;
F &= ~C_FLAG;
} else {
F &= ~H_FLAG;
F |= C_FLAG;
}
F &= ~N_FLAG;
/* S_FLAG, Z_FLAG, and P_FLAG unchanged */
break;
case 0x41: /* LD B,C */
B = C;
break;
case 0x42: /* LD B,D */
B = D;
break;
case 0x43: /* LD B,E */
B = E;
break;
case 0x44: /* LD B,irh */
B = IRH;
break;
case 0x45: /* LD B,irl */
B = IRL;
break;
case 0x46: /* LD B,(ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
B = memrdr(W);
t += 3;
break;
case 0x47: /* LD B,A */
B = A;
break;
case 0x48: /* LD C,B */
C = B;
break;
case 0x4a: /* LD C,D */
C = D;
break;
case 0x4b: /* LD C,E */
C = E;
break;
case 0x4c: /* LD C,irh */
C = IRH;
break;
case 0x4d: /* LD C,irl */
C = IRL;
break;
case 0x4e: /* LD C,(ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
C = memrdr(W);
t += 3;
break;
case 0x4f: /* LD C,A */
C = A;
break;
case 0x50: /* LD D,B */
D = B;
break;
case 0x51: /* LD D,C */
D = C;
break;
case 0x53: /* LD D,E */
D = E;
break;
case 0x54: /* LD D,irh */
D = IRH;
break;
case 0x55: /* LD D,irl */
D = IRL;
break;
case 0x56: /* LD D,(ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
D = memrdr(W);
t += 3;
break;
case 0x57: /* LD D,A */
D = A;
break;
case 0x58: /* LD E,B */
E = B;
break;
case 0x59: /* LD E,C */
E = C;
break;
case 0x5a: /* LD E,D */
E = D;
break;
case 0x5c: /* LD E,irh */
E = IRH;
break;
case 0x5d: /* LD E,irl */
E = IRL;
break;
case 0x5e: /* LD E,(ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
E = memrdr(W);
t += 3;
break;
case 0x5f: /* LD E,A */
E = A;
break;
case 0x60: /* LD irh,B */
IRH = B;
break;
case 0x61: /* LD irh,C */
IRH = C;
break;
case 0x62: /* LD irh,D */
IRH = D;
break;
case 0x63: /* LD irh,E */
IRH = E;
break;
case 0x65: /* LD irh,irl */
IRH = IRL;
break;
case 0x66: /* LD H,(ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
H = memrdr(W);
} else
IRH = memrdr(W);
t += 3;
break;
case 0x67: /* LD irh,A */
IRH = A;
break;
case 0x68: /* LD irl,B */
IRL = B;
break;
case 0x69: /* LD irl,C */
IRL = C;
break;
case 0x6a: /* LD irl,D */
IRL = D;
break;
case 0x6b: /* LD irl,E */
IRL = E;
break;
case 0x6c: /* LD irl,irh */
IRL = IRH;
break;
case 0x6e: /* LD L,(ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
L = memrdr(W);
} else
IRL = memrdr(W);
t += 3;
break;
case 0x6f: /* LD irl,A */
IRL = A;
break;
case 0x70: /* LD (ir),B */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
memwrt(W, B);
t += 3;
break;
case 0x71: /* LD (ir),C */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
memwrt(W, C);
t += 3;
break;
case 0x72: /* LD (ir),D */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
memwrt(W, D);
t += 3;
break;
case 0x73: /* LD (ir),E */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
memwrt(W, E);
t += 3;
break;
case 0x74: /* LD (ir),H */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
memwrt(W, H);
} else
memwrt(W, IRH);
t += 3;
break;
case 0x75: /* LD (ir),L */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
memwrt(W, L);
} else
memwrt(W, IRL);
t += 3;
break;
case 0x76: /* HALT */
// cry and die, no interrupts yet
State = Halted;
break;
case 0x77: /* LD (ir),A */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
memwrt(W, A);
t += 3;
break;
case 0x78: /* LD A,B */
A = B;
break;
case 0x79: /* LD A,C */
A = C;
break;
case 0x7a: /* LD A,D */
A = D;
break;
case 0x7b: /* LD A,E */
A = E;
break;
case 0x7c: /* LD A,irh */
A = IRH;
break;
case 0x7d: /* LD A,irl */
A = IRL;
break;
case 0x7e: /* LD A,(ir) */
W = IR;
if (curr_ir != IR_HL) {
W += (SBYTE) memrdr(PC++);
t += 8;
}
A = memrdr(W);
t += 3;
break;
case 0x80: /* ADD A,B */
P = B;