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chip_cmp.c
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chip_cmp.c
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#include <stdlib.h>
#include <string.h>
#include <stdio.h>
#include "stdtype.h"
#include "stdbool.h"
//#define REMOVE_NES_DPCM_0
// TODO: K053260, K054539 (for mega size reduction)
typedef struct sn76496_data
{
UINT8 FreqMSB[0x04];
UINT8 FreqLSB[0x04];
UINT8 VolData[0x04];
UINT8 LastReg;
bool LastRet;
} SN76496_DATA;
typedef struct ym2413_data
{
UINT8 RegData[0x40];
UINT8 RegFirst[0x40];
} YM2413_DATA;
typedef struct ym2612_data
{
UINT8 RegData[0x200];
UINT8 RegFirst[0x200];
UINT8 KeyOn[0x08];
UINT8 KeyFirst[0x08];
} YM2612_DATA;
typedef struct ym2151_data
{
UINT8 RegData[0x100];
UINT8 RegFirst[0x100];
UINT8 MCMask[0x08];
UINT8 MCFirst[0x08];
UINT8 MDMask[0x02]; // 0x00 - AMD, 0x01 - PMD
UINT8 MDFirst[0x02];
} YM2151_DATA;
typedef struct segapcm_data
{
UINT8* ROMData;
UINT8* ROMUsage;
UINT8 RAMData[0x800];
UINT8 RAMFirst[0x800];
UINT8 ChnPrg[0x10]; // channel is progressing
} SEGAPCM_DATA;
typedef struct rf5c68_channel
{
UINT8 ChnReg[0x07];
UINT8 RegFirst[0x07];
} RF5C68_CHANNEL;
#define RF_CBANK 0x00
#define RF_WBANK 0x01
#define RF_ENABLE 0x02
#define RF_CHN_MASK 0x03
#define RF_CHN_LOOP 0x04
typedef struct rf5c68_data
{
RF5C68_CHANNEL chan[0x08];
UINT8 RegData[0x05];
UINT8 RegFirst[0x05];
//UINT8 ChnSelLoopSave;
} RF5C68_DATA;
typedef struct ym2203_data
{
UINT8 RegData[0x100];
UINT8 RegFirst[0x100];
UINT8 KeyOn[0x04];
UINT8 KeyFirst[0x04];
UINT8 PreSclCmd;
} YM2203_DATA;
typedef struct ym2608_data
{
UINT8 RegData[0x200];
UINT8 RegFirst[0x200];
UINT8 KeyOn[0x08];
UINT8 KeyFirst[0x08];
UINT8 PreSclCmd;
} YM2608_DATA;
typedef struct ym2610_data
{
UINT8 RegData[0x200];
UINT8 RegFirst[0x200];
UINT8 KeyOn[0x08];
UINT8 KeyFirst[0x08];
UINT8 PreSclCmd;
} YM2610_DATA;
typedef struct ym3812_data
{
UINT8 RegData[0x100];
UINT8 RegFirst[0x100];
} YM3812_DATA;
typedef struct ym3526_data
{
UINT8 RegData[0x100];
UINT8 RegFirst[0x100];
} YM3526_DATA;
typedef struct y8950_data
{
UINT8 RegData[0x100];
UINT8 RegFirst[0x100];
} Y8950_DATA;
typedef struct ymf262_data
{
UINT8 RegData[0x200];
UINT8 RegFirst[0x200];
} YMF262_DATA;
typedef struct ymf278b_data
{
UINT8 RegData[0x300];
UINT8 RegFirst[0x300];
} YMF278B_DATA;
typedef struct ymf271_slot
{
UINT8 RegData[0x10];
UINT8 RegFirst[0x10];
UINT8 PCMRegFirst[0x10];
UINT8 PCMRegData[0x10];
/*UINT8 startaddr[3];
UINT8 loopaddr[3];
UINT8 endaddr[3];
UINT8 slotnote;
UINT8 sltnfirst;*/
} YMF271_SLOT;
typedef struct ymf271_group
{
UINT8 Data;
UINT8 First;
UINT8 sync;
} YMF271_GROUP;
typedef struct ymf271_chip
{
YMF271_SLOT slots[48];
YMF271_GROUP groups[12];
UINT8 TmrData[0x04];
UINT8 TmrFirst[0x04];
UINT8 ext_address[3];
UINT8 ext_read;
} YMF271_DATA;
/*typedef struct ymf278b_data
{
UINT8 RegData[0x300];
UINT8 RegFirst[0x300];
} YMF278B_DATA;*/
typedef struct ymz280b_data
{
UINT8 RegData[0x100];
UINT8 RegFirst[0x100];
UINT8 KeyOn[0x08];
} YMZ280B_DATA;
typedef struct ay8910_data
{
UINT8 RegData[0x10];
UINT8 RegFirst[0x10];
} AY8910_DATA;
typedef struct gameboy_dmg_data
{
UINT8 RegData[0x30];
UINT8 RegFirst[0x30];
} GBDMG_DATA;
typedef struct nes_apu_data
{
UINT8 RegData[0x80];
UINT8 RegFirst[0x80];
} NESAPU_DATA;
enum
{
C140_TYPE_SYSTEM2,
C140_TYPE_SYSTEM21,
C140_TYPE_ASIC219
};
typedef struct c140_data
{
UINT8 banking_type;
UINT8 RegData[0x200];
UINT8 RegFirst[0x200];
} C140_DATA;
typedef struct qsound_data
{
UINT16 RegData[0x100];
UINT8 RegFirst[0x100];
UINT8 KeyOn[0x10];
} QSOUND_DATA;
typedef struct pokey_data
{
UINT8 RegData[0x10];
UINT8 RegFirst[0x10];
} POKEY_DATA;
typedef struct huc6280_channel
{
UINT8 ChnReg[0x07];
UINT8 RegFirst[0x07];
} C6280_CHANNEL;
#define C6280_CHN_SEL 0x00
#define C6280_BALANCE 0x01
#define C6280_LFO_FRQ 0x02
#define C6280_LFO_CTRL 0x03
#define C6280_CHN_LOOP 0x04
typedef struct huc6280_data
{
C6280_CHANNEL chan[0x08]; // the chip has only 6 channels, but the register supports 8
UINT8 RegData[0x05];
UINT8 RegFirst[0x05];
//UINT8 ChnSelLoopSave;
} C6280_DATA;
#define K054539_RESET_FLAGS 0x00
#define K054539_REVERSE_STEREO 0x01
#define K054539_DISABLE_REVERB 0x02
#define K054539_UPDATE_AT_KEYON 0x04
typedef struct k054539_data
{
UINT8 RegData[0x230];
UINT8 RegFirst[0x230];
// UINT8 k054539_flags;
} K054539_DATA;
typedef struct k051649_data
{
UINT8 WaveData[0x20 * 5];
UINT8 WaveFirst[0x20 * 5];
UINT8 FreqData[0x02 * 5];
UINT8 FreqFirst[0x02 * 5];
UINT8 VolData[0x01 * 5];
UINT8 VolFirst[0x01 * 5];
UINT8 KeyOn;
UINT8 KeyFirst;
} K051649_DATA;
typedef struct okim6295_data
{
UINT8 RegData[0x14];
UINT8 RegFirst[0x14];
} OKIM6295_DATA;
typedef struct okim6295_data OKIM6258_DATA;
typedef struct upd7759_data
{
UINT8 RegData[0x04];
UINT8 RegFirst[0x04];
} UPD7759_DATA;
#define C352_FLG_LINKLOOP 0x0022
typedef struct c352_data
{
UINT16 RegData[0x208];
UINT8 RegFirst[0x208];
} C352_DATA;
typedef struct x1_010_data
{
UINT8 RegData[0x2000];
UINT8 RegFirst[0x2000];
} X1_010_DATA;
typedef struct es5503_data
{
UINT8 RegData[0xE2];
UINT8 RegFirst[0xE2];
} ES5503_DATA;
typedef struct wonderswan_data
{
UINT8 RegData[0x20];
UINT8 RegFirst[0x20];
} WSWAN_DATA;
typedef struct vsu_data
{
UINT8 RegData[0x160];
UINT8 RegFirst[0x160];
} VSU_DATA;
typedef struct all_chips
{
UINT8 GGSt;
SN76496_DATA SN76496;
YM2413_DATA YM2413;
YM2612_DATA YM2612;
YM2151_DATA YM2151;
SEGAPCM_DATA SegaPCM;
RF5C68_DATA RF5C68;
YM2203_DATA YM2203;
YM2608_DATA YM2608;
YM2610_DATA YM2610;
YM3812_DATA YM3812;
YM3526_DATA YM3526;
Y8950_DATA Y8950;
YMF262_DATA YMF262;
YMF278B_DATA YMF278B;
YMF271_DATA YMF271;
//YMF278B_DATA YMF278B;
YMZ280B_DATA YMZ280B;
RF5C68_DATA RF5C164;
AY8910_DATA AY8910;
GBDMG_DATA GBDMG;
NESAPU_DATA NES;
UPD7759_DATA UPD7759;
OKIM6258_DATA OKIM6258;
OKIM6295_DATA OKIM6295;
K051649_DATA K051649;
K054539_DATA K054539;
C6280_DATA C6280;
C140_DATA C140;
POKEY_DATA Pokey;
QSOUND_DATA QSound;
//SCSP_DATA SCSP;
ES5503_DATA ES5503;
C352_DATA C352;
X1_010_DATA X1_010;
WSWAN_DATA WSwan;
VSU_DATA VSU;
} ALL_CHIPS;
void InitAllChips(void);
void ResetAllChips(void);
void FreeAllChips(void);
void SetChipSet(UINT8 ChipID);
bool dac_stream_control_freq(UINT8 strmID, UINT32 freq);
bool GGStereo(UINT8 Data);
bool sn76496_write(UINT8 Command/*, UINT8 NextCmd*/);
bool ym2413_write(UINT8 Register, UINT8 Data);
bool ym2612_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool ym2151_write(UINT8 Register, UINT8 Data);
bool segapcm_mem_write(UINT16 Offset, UINT8 Data);
static bool rf_pcm_reg_write(RF5C68_DATA* chip, UINT8 Register, UINT8 Data);
bool rf5c68_reg_write(UINT8 Register, UINT8 Data);
bool ym2203_write(UINT8 Register, UINT8 Data);
bool ym2608_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool ym2610_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool ym3812_write(UINT8 Register, UINT8 Data);
bool ym3526_write(UINT8 Register, UINT8 Data);
bool y8950_write(UINT8 Register, UINT8 Data);
bool ymf262_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool ymf278b_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool ymz280b_write(UINT8 Register, UINT8 Data);
bool rf5c164_reg_write(UINT8 Register, UINT8 Data);
static bool ay8910_part_write(UINT8* RegData, UINT8* RegFirst, UINT8 Register, UINT8 Data);
bool ay8910_write_reg(UINT8 Register, UINT8 Data);
static bool ymf271_write_fm_reg(YMF271_DATA* chip, UINT8 SlotNum, UINT8 Register, UINT8 Data);
static bool ymf271_write_fm(YMF271_DATA* chip, UINT8 Port, UINT8 Register, UINT8 Data);
bool ymf271_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool gameboy_write_reg(UINT8 Register, UINT8 Data);
static bool ymdeltat_write(UINT8 Register, UINT8 Data, UINT8* RegData, UINT8* RegFirst);
bool nes_psg_write(UINT8 Register, UINT8 Data);
bool c140_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool qsound_write(UINT8 Offset, UINT16 Value);
bool pokey_write(UINT8 Register, UINT8 Data);
static bool fmadpcm_write(UINT8 Register, UINT8 Data, UINT8* RegData, UINT8* RegFirst);
bool k054539_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool k051649_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool scsp_write(UINT8 Port, UINT8 Register, UINT8 Data);
bool okim6295_write(UINT8 Port, UINT8 Data);
bool upd7759_write(UINT8 Port, UINT8 Data);
bool okim6258_write(UINT8 Port, UINT8 Data);
bool c352_write(UINT16 Offset, UINT16 Value);
bool x1_010_write(UINT16 Offset, UINT8 Value);
bool es5503_write(UINT8 Register, UINT8 Data);
bool vsu_write(UINT16 Register, UINT8 Data);
bool wswan_write(UINT8 Register, UINT8 Data);
// Function Prototypes from vgm_cmp.c
bool GetNextChipCommand(void);
UINT8 ChipCount = 0x02;
ALL_CHIPS* ChipData = NULL;
ALL_CHIPS* ChDat;
UINT32 StreamFreqs[0x100];
extern bool JustTimerCmds;
extern bool DoOKI6258;
extern UINT16 NxtCmdReg;
extern UINT8 NxtCmdVal;
bool VGM_Loops;
void InitAllChips(void)
{
UINT8 CurChip;
ALL_CHIPS* TempChp;
if (ChipData == NULL)
ChipData = (ALL_CHIPS*)malloc(ChipCount * sizeof(ALL_CHIPS));
for (CurChip = 0x00; CurChip < ChipCount; CurChip ++)
{
TempChp = &ChipData[CurChip];
memset(TempChp, 0xFF, sizeof(ALL_CHIPS));
TempChp->GGSt = 0x00;
memset(TempChp->SegaPCM.ChnPrg, 0x00, sizeof(UINT8) * 0x10);
// FM ADPCM restarts notes always, so leaving them at FF works fine.
//TempChp->YM2608.RegData[0x010] = 0x00;
//TempChp->YM2610.RegData[0x100] = 0x00;
memset(TempChp->YMZ280B.KeyOn, 0x00, sizeof(UINT8) * 0x08);
TempChp->C140.banking_type = 0x00;
memset(TempChp->QSound.KeyOn, 0x00, sizeof(UINT8) * 0x10);
memset(&TempChp->OKIM6258.RegFirst[0x08], 0x00, 0x0D-0x08);
memset(TempChp->WSwan.RegData, 0x00, 0x20);
}
memset(StreamFreqs, 0xFF, sizeof(UINT32) * 0x100);
VGM_Loops = false;
SetChipSet(0x00);
return;
}
void ResetAllChips(void)
{
UINT8 CurChip;
ALL_CHIPS* TempChp;
UINT8 RegBak[0x05];
UINT8 ClkBak[0x05];
UINT8 VSUBak[0x60];
for (CurChip = 0x00; CurChip < ChipCount; CurChip ++)
{
TempChp = &ChipData[CurChip];
RegBak[0x00] = TempChp->RF5C68.RegData[RF_CBANK];
RegBak[0x01] = TempChp->RF5C164.RegData[RF_CBANK];
RegBak[0x02] = TempChp->C6280.RegData[C6280_CHN_SEL];
RegBak[0x03] = TempChp->C140.banking_type;
//RegBak[0x03] = TempChp->YM2608.RegData[0x010];
//RegBak[0x04] = TempChp->YM2610.RegData[0x100];
memcpy(ClkBak, &TempChp->OKIM6258.RegData[0x08], 0x05);
memcpy(VSUBak, &TempChp->VSU.RegData[0x100], 0x60);
// TODO: reset RegFist for each chip separately
memset(TempChp, 0xFF, sizeof(ALL_CHIPS));
TempChp->GGSt = 0x00;
memset(TempChp->SegaPCM.ChnPrg, 0x00, sizeof(UINT8) * 0x10);
memset(TempChp->YMZ280B.KeyOn, 0x00, sizeof(UINT8) * 0x08);
TempChp->C140.banking_type = RegBak[0x03];
memset(TempChp->QSound.KeyOn, 0x00, sizeof(UINT8) * 0x10);
TempChp->RF5C68.RegData[RF_CBANK] = RegBak[0x00];
TempChp->RF5C68.RegData[RF_CHN_LOOP] = RegBak[0x00];
TempChp->RF5C164.RegData[RF_CBANK] = RegBak[0x01];
TempChp->RF5C164.RegData[RF_CHN_LOOP] = RegBak[0x01];
TempChp->C6280.RegData[C6280_CHN_SEL] = RegBak[0x02];
TempChp->C6280.RegData[C6280_CHN_LOOP] = RegBak[0x02];
//TempChp->YM2608.RegData[0x010] = RegBak[0x03];
//TempChp->YM2610.RegData[0x100] = RegBak[0x04];
memcpy(&TempChp->OKIM6258.RegData[0x08], ClkBak, 0x05);
memcpy(&TempChp->VSU.RegData[0x100], VSUBak, 0x60);
}
memset(StreamFreqs, 0xFF, sizeof(UINT32) * 0x100);
VGM_Loops = true;
return;
}
void FreeAllChips(void)
{
if (ChipData == NULL)
return;
free(ChipData);
ChipData = NULL;
return;
}
void SetChipSet(UINT8 ChipID)
{
ChDat = ChipData + ChipID;
return;
}
bool dac_stream_control_freq(UINT8 strmID, UINT32 freq)
{
if (JustTimerCmds)
return true;
if (freq == StreamFreqs[strmID])
return false;
StreamFreqs[strmID] = freq;
return true;
}
bool GGStereo(UINT8 Data)
{
if (Data == ChDat->GGSt && ! JustTimerCmds)
return false;
ChDat->GGSt = Data;
return true;
}
bool sn76496_write(UINT8 Command/*, UINT8 NextCmd*/)
{
SN76496_DATA* chip;
UINT8 Channel;
UINT8 Reg;
UINT8 Data;
bool RetVal;
UINT8 NextCmd;
if (JustTimerCmds)
return true;
chip = &ChDat->SN76496;
RetVal = GetNextChipCommand();
NextCmd = RetVal ? NxtCmdVal : 0x80;
RetVal = true;
if (Command & 0x80)
{
Reg = (Command & 0x70) >> 4;
Channel = Reg >> 1;
Data = Command & 0x0F;
chip->LastReg = Reg;
switch(Reg)
{
case 0: // Tone 0: Frequency
case 2: // Tone 1: Frequency
case 4: // Tone 2: Frequency
if (Data == chip->FreqMSB[Channel])
{
if (NextCmd & 0x80)
{
// Next command doesn't depend on the current one
RetVal = false;
}
else
{
Data = NextCmd & 0x7F; // NextCmd & 0x3F
if (Data == chip->FreqLSB[Channel])
RetVal = false;
}
}
else
{
chip->FreqMSB[Channel] = Data;
}
break;
case 6: // Noise: Frequency, Mode
return true; // a Noise Mode write resets the Noise Shifter
case 1: // Tone 0: Volume
case 3: // Tone 1: Volume
case 5: // Tone 2: Volume
case 7: // Noise: Volume
if ((Command & 0x0F) == chip->VolData[Channel])
{
if (NextCmd & 0x80)
{
// Next command doesn't depend on the current one
RetVal = false;
}
else
{
Data = NextCmd & 0x0F;
if (Data == chip->VolData[Channel])
RetVal = false;
printf("Warning! Data Command after Volume Command!\n");
}
}
else
{
chip->VolData[Channel] = Data;
}
break;
}
}
else
{
Reg = chip->LastReg;
Channel = Reg >> 1;
Data = Command & 0x7F; // Command & 0x3F
if (! (Reg & 0x10))
{
if (Data == chip->FreqLSB[Channel])
RetVal = chip->LastRet; // remove event only, if previous event was removed
else
chip->FreqLSB[Channel] = Data;
}
else
{
// I still handle this correctly
if (Data == chip->VolData[Channel])
RetVal = chip->LastRet;
else
chip->VolData[Channel] = Data;
}
}
chip->LastRet = RetVal;
//if (Channel != 0x00)
//if (Channel != 0x01)
//if (Channel != 0x02 || (ChDat != ChipData && !(Reg & 0x01)))
//if (! (Channel == 0x03 || (ChDat != ChipData && Channel == 0x02 && !(Reg & 0x01))))
// RetVal = false;
return RetVal;
}
bool ym2413_write(UINT8 Register, UINT8 Data)
{
YM2413_DATA* chip = &ChDat->YM2413;
Register &= 0x3F;
if (! chip->RegFirst[Register] && Data == chip->RegData[Register])
return false;
chip->RegFirst[Register] = JustTimerCmds;
chip->RegData[Register] = Data;
return true;
}
bool ym2612_write(UINT8 Port, UINT8 Register, UINT8 Data)
{
YM2612_DATA* chip = &ChDat->YM2612;
UINT16 RegVal;
UINT8 Channel;
RegVal = (Port << 8) | Register;
switch(RegVal)
{
// no OPN Prescaler Registers for YM2612
case 0x027:
Data &= 0xC3; // mask out all timer-relevant bits except general 'enable' bits
if (! chip->RegFirst[RegVal] && Data == chip->RegData[RegVal])
return false;
chip->RegFirst[RegVal] = 0x00;
chip->RegData[RegVal] = Data;
break;
case 0x028:
Channel = Data & 0x07;
if (! chip->KeyFirst[Channel] && Data == chip->KeyOn[Channel])
return false;
chip->KeyFirst[Channel] = JustTimerCmds;
chip->KeyOn[Channel] = Data;
break;
case 0x02A:
/*// Hack for Pier Solar Beta
// Remove every 2nd DAC command (because every DAC command is sent 2 times)
// this includes a check and a warning output
chip->RegFirst[RegVal] ^= 0x01;
if (chip->RegFirst[RegVal] & 0x01)
{
if (Data == chip->RegData[RegVal])
return false;
else //if (Data != chip->RegData[RegVal])
printf("Warning! DAC Compression failed!\n");
}
chip->RegData[RegVal] = Data;*/
return true; // I leave this on for later optimizations
default:
// no SSG emulator for YM2612
switch(RegVal & 0xF4)
{
case 0xA0: // A0-A3 and A8-AB
if ((RegVal & 0x03) == 0x03)
break;
if (! chip->RegFirst[RegVal] && Data == chip->RegData[RegVal])
return false;
chip->RegFirst[RegVal] = JustTimerCmds;
chip->RegData[RegVal] = Data;
return true;
case 0xA4: // A4-A7 and AC-AF - Frequence Latch
if ((RegVal & 0x03) == 0x03)
break;
// FINALLY, I got it to work properly
// The vgm I tested (Dyna Brothers 2 - 28 - Get Crazy - More Rave.vgz) was
// successfully tested against the Gens and MAME cores.
while(GetNextChipCommand())
{
if ((NxtCmdReg & 0x1FC) == (RegVal & 0x1FC))
{
return false; // this will be ignored, because the A0 write is missing
}
else if ((NxtCmdReg & 0x1FF) == (RegVal & 0x1FB))
{
if (chip->RegFirst[RegVal])
{
chip->RegFirst[RegVal] = JustTimerCmds;
chip->RegData[RegVal] = Data;
chip->RegFirst[RegVal & 0x1FB] = 0x01;
return true;
}
else if (chip->RegData[RegVal] == Data &&
chip->RegData[RegVal & 0x1FB] == NxtCmdVal)
{
chip->RegFirst[RegVal] = JustTimerCmds;
chip->RegData[RegVal] = Data;
chip->RegFirst[RegVal & 0x1FB] = JustTimerCmds;
return false;
}
else
{
chip->RegFirst[RegVal] = JustTimerCmds;
chip->RegData[RegVal] = Data;
chip->RegFirst[RegVal & 0x1FB] = 0x01;
return true;
}
}
}
chip->RegData[RegVal] = Data;
return true;
}
if (! chip->RegFirst[RegVal] && Data == chip->RegData[RegVal])
return false;
chip->RegFirst[RegVal] = JustTimerCmds;
chip->RegData[RegVal] = Data;
break;
}
return true;
}
bool ym2151_write(UINT8 Register, UINT8 Data)
{
YM2151_DATA* chip = &ChDat->YM2151;
UINT8 Channel;
switch(Register)
{
case 0x08: // Key On state
Channel = Data & 0x07;
Data &= 0xF8;
if (! chip->MCFirst[Channel] && Data == chip->MCMask[Channel])
return false;
chip->MCFirst[Channel] = JustTimerCmds;
chip->MCMask[Channel] = Data;
break;
case 0x14:
Data &= 0x83; // mask out all timer-relevant bits except general 'enable' bits
if (! chip->RegFirst[Register] && Data == chip->RegData[Register])
return false;
chip->RegFirst[Register] = 0x00;
chip->RegData[Register] = Data;
break;
case 0x19: // AMD / PMD
Channel = (Data & 0x80) >> 7;
Data &= 0x7F;
if (! chip->MDFirst[Channel] && Data == chip->MDMask[Channel])
return false;
chip->MDFirst[Channel] = JustTimerCmds;
chip->MDMask[Channel] = Data;
break;
default:
// Timer registers (0x10/0x11/0x12) are intentionally kept (for e.g. CSM)
if (! chip->RegFirst[Register] && Data == chip->RegData[Register])
return false;
chip->RegFirst[Register] = JustTimerCmds;
chip->RegData[Register] = Data;
break;
}
return true;
}
bool segapcm_mem_write(UINT16 Offset, UINT8 Data)
{
SEGAPCM_DATA* chip = &ChDat->SegaPCM;
UINT8 Channel;
UINT16 RelOffset;
Offset &= 0x07FF; // it has 2 KB of RAM, but only 256 Byte are used
Channel = (Offset >> 3) & 0xF;
RelOffset = Offset & ~0x78;
if (RelOffset == 0x04 || RelOffset == 0x05)
RelOffset |= 0x80; // patch for the old SegaPCM core
switch(RelOffset)
{
case 0x07: // Sample Delta Time
if (! chip->RAMFirst[Offset] && Data == chip->RAMData[Offset])
return false;
// if Sample Delta Time is 0x00, it's like a KeyOff
chip->ChnPrg[Channel] &= ~0x02;
chip->ChnPrg[Channel] |= Data ? 0x02 : 0x00;
if (chip->ChnPrg[Channel] == 0x03)
{
chip->RAMFirst[(Channel << 3) | 0x84] |= 0x01;
chip->RAMFirst[(Channel << 3) | 0x85] |= 0x01;
chip->RAMFirst[(Channel << 3) | 0x86] |= 0x01;
chip->RAMFirst[(Channel << 3) | 0x04] |= 0x01;
chip->RAMFirst[(Channel << 3) | 0x05] |= 0x01;
}
chip->RAMFirst[Offset] = JustTimerCmds;
chip->RAMData[Offset] = Data;
break;
case 0x84: // Current Address L
case 0x85: // Current Address H
if (! chip->RAMFirst[Offset] && Data == chip->RAMData[Offset])
return false;
// the chip modifies the Current Address while playing,
// so they must be rewritten of a channel is active
chip->RAMFirst[Offset] = JustTimerCmds | (chip->ChnPrg[Channel] == 0x03);
chip->RAMData[Offset] = Data;
break;
case 0x86: // Channel Disable (Bit 0), Loop Disable (Bit 1), Bank
if (! chip->RAMFirst[Offset] && Data == chip->RAMData[Offset])
return false;
chip->ChnPrg[Channel] &= ~0x01;
chip->ChnPrg[Channel] |= (~Data & 0x01);
if (chip->ChnPrg[Channel] == 0x03)
{
// the Current Address registers must be written the next time
chip->RAMFirst[(Channel << 3) | 0x84] |= 0x01;
chip->RAMFirst[(Channel << 3) | 0x85] |= 0x01;
chip->RAMFirst[(Channel << 3) | 0x04] |= 0x01;
chip->RAMFirst[(Channel << 3) | 0x05] |= 0x01;
}
// like above, the Channel register gets modified by the chip,
// so the same rules apply
chip->RAMFirst[Offset] = JustTimerCmds | (chip->ChnPrg[Channel] == 0x03);
chip->RAMData[Offset] = Data;
break;
default:
if (! chip->RAMFirst[Offset] && Data == chip->RAMData[Offset])
return false;
chip->RAMFirst[Offset] = JustTimerCmds;
chip->RAMData[Offset] = Data;
break;
}
return true;
}
static bool rf_pcm_reg_write(RF5C68_DATA* chip, UINT8 Register, UINT8 Data)
{
RF5C68_CHANNEL* chan;
UINT8 OldVal;
switch(Register)
{
case 0x00: // Envelope
case 0x01: // Pan
case 0x02: // FD Low / step
case 0x03: // FD High / step
case 0x04: // Loop Start Low
case 0x05: // Loop Start High
case 0x06: // Start
chan = &chip->chan[chip->RegData[RF_CBANK] & 0x07];
if (chip->RegFirst[RF_CHN_LOOP])
chip->RegFirst[RF_CHN_LOOP] = 0x00;
if (Register == 0x06)
{
OldVal = chip->RegData[RF_CHN_MASK] & (0x01 << (chip->RegData[RF_CBANK] & 0x07));
if (! OldVal)
chan->RegFirst[Register] = 0x01;
}
if (! chan->RegFirst[Register] && Data == chan->ChnReg[Register])
return false;
chan->RegFirst[Register] = JustTimerCmds;
chan->ChnReg[Register] = Data;
break;
case 0x07: // Control Register
OldVal = chip->RegData[RF_ENABLE];
if (Data & 0x40)
OldVal |= chip->RegData[RF_CBANK];
else
OldVal |= chip->RegData[RF_WBANK];
if (! chip->RegFirst[RF_ENABLE] && Data == OldVal)
return false;
if (/*! chip->RegFirst[RF_ENABLE] &&*/ (Data & 0x40))
{
// additional test for 2 Channel Select-Commands after each other
// that makes first one useless, of course :)
OldVal = 0x00;
while(GetNextChipCommand())
{
if (NxtCmdReg <= 0x06)
{
OldVal = 0x01;
break;
}
else if (NxtCmdReg == 0x07 && (NxtCmdVal & 0x40))
{
return false;
}
}
if (! OldVal)
{
// see HuC6280 section for notes for this if
if (! VGM_Loops || (chip->RegFirst[RF_CHN_LOOP] ||
chip->RegData[RF_CHN_LOOP] == 0x80))
{
// when no command follows the Channel Select one, it's useless too
return false;
}
}
}
chip->RegFirst[RF_ENABLE] = JustTimerCmds;
chip->RegData[RF_ENABLE] = Data & 0x80;
if (Data & 0x40)
{
chip->RegData[RF_CBANK] = Data;
if (chip->RegFirst[RF_CHN_LOOP])
{
// is the Channel Select the first command after the loop?
chip->RegFirst[RF_CHN_LOOP] = 0x00;
chip->RegData[RF_CHN_LOOP] = 0x80; // set to 'ignore'
}
}
else
{
chip->RegData[RF_WBANK] = Data;
}
break;
case 0x08: // Channel On/Off Register
if (! chip->RegFirst[RF_CHN_MASK] && Data == chip->RegData[RF_CHN_MASK])
return false;
chip->RegFirst[RF_CHN_MASK] = JustTimerCmds;
chip->RegData[RF_CHN_MASK] = Data;
break;
}
return true;
}
bool rf5c68_reg_write(UINT8 Register, UINT8 Data)
{
RF5C68_DATA* chip = &ChDat->RF5C68;
return rf_pcm_reg_write(chip, Register, Data);
}
bool ym2203_write(UINT8 Register, UINT8 Data)
{
YM2203_DATA* chip = &ChDat->YM2203;
UINT8 Channel;
/*if ((Register & 0x1F0) == 0x000)
return ! (Register >= 0x0E && Register <= 0x0F);
else
return false;*/
switch(Register)
{
case 0x27:
Data &= 0xC3; // mask out all timer-relevant bits except general 'enable' bits
if (! chip->RegFirst[Register] && Data == chip->RegData[Register])
return false;
chip->RegFirst[Register] = 0x00;
chip->RegData[Register] = Data;
break;
case 0x2D: // OPN Prescaler Registers
case 0x2E:
case 0x2F:
if (chip->PreSclCmd == Register)
return false;
chip->PreSclCmd = Register;
break;
case 0x28:
Channel = Data & 0x03;
if (! chip->KeyFirst[Channel] && Data == chip->KeyOn[Channel])
return false;
chip->KeyFirst[Channel] = JustTimerCmds;
chip->KeyOn[Channel] = Data;
break;
default:
if ((Register & 0x1F0) == 0x000)
{
// SSG emulator (AY8910)
return ay8910_part_write(chip->RegData, chip->RegFirst, Register & 0x0F, Data);
}
switch(Register & 0xF4)
{
case 0xA0: // A0-A3 and A8-AB
if ((Register & 0x03) == 0x03)