Skip to content
View vijayank88's full-sized avatar
  • https://www.chipwaretechnologies.com/
  • Bengaluru,India
  • 16:17 (UTC +05:30)
  • X @VijayanKris

Block or report vijayank88

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
vijayank88/README.md
  • 👋 Hi, I’m @vijayank88
  • 👀 I’m interested in ... HDL coding, Front end flow, Back end flow
  • 🌱 I’m currently learning ... HDL colding
  • 💞️ I’m looking to collaborate on ...
  • 📫 How to reach me ...

Popular repositories Loading

  1. OpenROAD-flow-scripts OpenROAD-flow-scripts Public

    Forked from The-OpenROAD-Project/OpenROAD-flow-scripts

    Verilog 2 1

  2. graphics_controller graphics_controller Public

    Verilog 2

  3. OpenROAD OpenROAD Public

    Forked from The-OpenROAD-Project/OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow

    Verilog 1

  4. Verilog_RTL Verilog_RTL Public

    Forked from VenuPabbuleti/100-Days-RTL-using-Verilog

    RTL Design using Verilog Hardware Description Language

    Verilog 1

  5. vijayank88 vijayank88 Public

    Config files for my GitHub profile.

  6. OpenRAM OpenRAM Public

    Forked from VLSIDA/OpenRAM

    An open-source static random access memory (SRAM) compiler.

    Python