| Discipline | Engineering |
|---|---|
| Lab | Digital Electronics |
| Experiment | 10. Design and verify the 4- Bit Synchronous/ Asynchronous Counter using JK flip flop. |
This experiment is to verify the truth table and timing diagram of 4-bit synchronous parallel counter and 4-bit asynchronous parallel counter by using JK flip flop ICs and analyse the circuit of 4-bit synchronous parallel counter and 4-bit asynchronous parallel counter with the help of LEDs display.
| Name of Developer | R.S. Anand |
|---|---|
| Institute | IIT Roorkee |
| Email id | anandfee@gmail.com |
| Department | Electrical Engineering |
| SrNo | Name | Faculty or Student | Department | Institute | Email id |
|---|---|---|---|---|---|
| 1 | R.S. Anand | Faculty | Electrical Engineering | IIT Roorkee, Roorkee | anandfee@gmail.com |
| 2 | Jasbir Singh | Research Fellow | Electrical Engineering | IIT Roorkee, Roorkee | jasbirjassy6@gmail.com |
| 3 | Rajeev Kumar | Research Fellow | Electrical Engineering | IIT Roorkee, Roorkee | rajeevkumar.rke@gmail.com |
| 4 | Priyanshi Agarwal | Research Fellow | Electrical Engineering | IIT Roorkee, Roorkee | priyanshi.a07@gmail.com |