Merge branch 'develop' into 'main'

Meeting memory mode selection See merge request racetrack-logic/risc-v-lim-architecture!14
vlsi-nanocomputing · Aug 29, 2022 · 84cac5a · 84cac5a
2 parents 0db3f17 + 4bafe0b
commit 84cac5a
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Showing 4 changed files with 29 additions and 11 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -9,7 +9,7 @@ build_vsim_mem_std_mode0:
   - git submodule update --remote RI5CY-sameIF/rtl/fpnew
   - cd RI5CY-sameIF/tb/core
   - source /eda/scripts/init_questa_core_prime
-  - make RISCV_LIB=/opt/riscv-rv32ima-ilp32 MEM_MODE=0 MEM_TYPE=STD_MEM custom-vsim-run
+  - make RISCV_LIB=/opt/riscv-rv32ima-ilp32 MEM_MODE=MODE_0 MEM_TYPE=STD_MEM custom-vsim-run
 
 #build_vcs_lim_mem:
 # stage: vcs_lim_mem

diff --git a/README.md b/README.md
@@ -46,13 +46,13 @@ Enter the directory `RI5CY-sameIF/tb/core` and modify the Makefile. In particula
 
 Modify variable `MEM_TYPE` inside the Makefile to build the desired memory type.
 Available memories:
-- Standard memory (STD_MEM)
-- Standard memory with LiM functionalities (LIM_MEM)
-- Racetrack memory with LiM functionalities (RT_LIM_MEM)
+- Standard memory (MEM_TYPE = STD_MEM)
+- Standard memory with LiM functionalities (MEM_TYPE = LIM_MEM)
+- Racetrack memory with LiM functionalities (MEM_TYPE = RT_LIM_MEM)
 
-Racetrack memory supports two different modes, set the correct parameter `MEM_MODE` in file `RI5CY-sameIF/tb/core/tb_tob.sv` to choose the wanted configuration:
-- Memory mode (MEM_MODE = 0)
-- LiM mode    (MEM_MODE = 1)
+Racetrack memory supports two different modes, modify variable `MEM_MODE` inside the Makefile to choose the wanted configuration:
+- Memory mode (MEM_MODE = MODE_0)
+- LiM mode    (MEM_MODE = MODE_1)
 
 
 

diff --git a/RI5CY-sameIF/tb/core/Makefile b/RI5CY-sameIF/tb/core/Makefile
@@ -117,6 +117,13 @@ MEM_TYPE    = RT_LIM_MEM
 #LIM_MEM    = compile standard memory with LiM functionalities
 #RT_LIM_MEM = compile Racetrack memory with/without LiM functionalities
 
+# Racetrack memory operational mode
+
+MEM_MODE    = MODE_0
+
+# MODE_0 = Work as a standard memory
+# MODE_1 = work as a LiM architecture
+
 
 
 # ===================================================================
@@ -138,7 +145,7 @@ vlib: .lib-rtl
 
 # rebuild if we change some sourcefile
 .build-rtl: .lib-rtl $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)
-	$(VLOG) +define+$(MEM_TYPE) -work $(VWORK) +incdir+$(RTLSRC_INCDIR) $(VLOG_FLAGS) \
+	$(VLOG) +define+$(MEM_TYPE) +define+$(MEM_MODE) -work $(VWORK) +incdir+$(RTLSRC_INCDIR) $(VLOG_FLAGS) \
 	$(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)
 	touch .build-rtl
 
@@ -176,7 +183,7 @@ vcsify: $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)
 		-timescale=1ns/1ns -j20\
 		-CC "-I$(VCS_HOME)/include -O3 -march=native" $(VCS_FLAGS) \
 		$(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)\
-		+incdir+$(RTLSRC_INCDIR) +define+$(MEM_TYPE)
+		+incdir+$(RTLSRC_INCDIR) +define+$(MEM_TYPE) +define+$(MEM_MODE)
 
 #STANDARD PROGRAMS (MEM_TYPE=STD_MEM)
 

diff --git a/RI5CY-sameIF/tb/core/tb_top.sv b/RI5CY-sameIF/tb/core/tb_top.sv
@@ -17,13 +17,23 @@
 module tb_top
     #(parameter INSTR_RDATA_WIDTH = 32,
       parameter RAM_ADDR_WIDTH = 22,
-      parameter MEM_MODE = 1,    //working mode for RT memory 1=LiM, 0=std 
       parameter BOOT_ADDR  = 'h180,
       parameter PULP_CLUSTER = 0,
       parameter FPU = 0,
       parameter PULP_ZFINX = 0,
       parameter DM_HALTADDRESS = 32'h1A110800);
 
+    //Set MEM_MODE parameter for Racetrack
+    `ifdef MODE_1
+
+    localparam MEM_MODE = 1;
+
+    `elsif MODE_0
+
+    localparam MEM_MODE = 0;
+
+    `endif 
+
     // comment to record execution trace
     //`define TRACE_EXECUTION
 
@@ -136,7 +146,8 @@ module tb_top
                          $time, firmware);
             $readmemh(firmware, riscv_wrapper_i.ram_i.dp_ram_i.mem);
 
-
+
+
     ///////////////////////////
     // Racetrack memory initialization
     ///////////////////////////