From 9fba7f1f00b6cb6673d7e8a32a94b94965804ca4 Mon Sep 17 00:00:00 2001 From: Gianluca Goti Date: Tue, 23 Aug 2022 19:57:58 +0200 Subject: [PATCH 1/7] Added Makefile variable for mem_mode parameter --- RI5CY-sameIF/tb/core/Makefile | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/RI5CY-sameIF/tb/core/Makefile b/RI5CY-sameIF/tb/core/Makefile index 29bb694..da0dae5 100644 --- a/RI5CY-sameIF/tb/core/Makefile +++ b/RI5CY-sameIF/tb/core/Makefile @@ -117,6 +117,13 @@ MEM_TYPE = RT_LIM_MEM #LIM_MEM = compile standard memory with LiM functionalities #RT_LIM_MEM = compile Racetrack memory with/without LiM functionalities +# Racetrack memory operational mode + +MEM_MODE = MODE_0 + +# MODE_0 = Work as a standard memory +# MODE_1 = work as a LiM architecture + # =================================================================== @@ -138,7 +145,7 @@ vlib: .lib-rtl # rebuild if we change some sourcefile .build-rtl: .lib-rtl $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT) - $(VLOG) +define+$(MEM_TYPE) -work $(VWORK) +incdir+$(RTLSRC_INCDIR) $(VLOG_FLAGS) \ + $(VLOG) +define+$(MEM_TYPE) +define+$(MEM_MODE) -work $(VWORK) +incdir+$(RTLSRC_INCDIR) $(VLOG_FLAGS) \ $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT) touch .build-rtl @@ -176,7 +183,7 @@ vcsify: $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT) -timescale=1ns/1ns -j20\ -CC "-I$(VCS_HOME)/include -O3 -march=native" $(VCS_FLAGS) \ $(RTLSRC_PKG) $(RTLSRC) $(RTLSRC_TB_PKG) $(RTLSRC_TB) $(RTLSRC_TB_RT)\ - +incdir+$(RTLSRC_INCDIR) +define+$(MEM_TYPE) + +incdir+$(RTLSRC_INCDIR) +define+$(MEM_TYPE) +define+$(MEM_MODE) #STANDARD PROGRAMS (MEM_TYPE=STD_MEM) From d72365cf18c10ac1f46b7c9161cb511425939717 Mon Sep 17 00:00:00 2001 From: Gianluca Goti Date: Tue, 23 Aug 2022 20:01:43 +0200 Subject: [PATCH 2/7] Modified tb_top, now mem_mode is set from Makefile --- RI5CY-sameIF/tb/core/tb_top.sv | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/RI5CY-sameIF/tb/core/tb_top.sv b/RI5CY-sameIF/tb/core/tb_top.sv index ab58f5e..274fbcc 100644 --- a/RI5CY-sameIF/tb/core/tb_top.sv +++ b/RI5CY-sameIF/tb/core/tb_top.sv @@ -17,13 +17,24 @@ module tb_top #(parameter INSTR_RDATA_WIDTH = 32, parameter RAM_ADDR_WIDTH = 22, - parameter MEM_MODE = 1, //working mode for RT memory 1=LiM, 0=std parameter BOOT_ADDR = 'h180, parameter PULP_CLUSTER = 0, parameter FPU = 0, parameter PULP_ZFINX = 0, parameter DM_HALTADDRESS = 32'h1A110800); + //Set MEM_MODE parameter for Racetrack + `ifdef MODE_1 + + localparam MEM_MODE = 1; + + `elsif MODE_0 + + localparam MEM_MODE = 0; + + `endif + + // comment to record execution trace //`define TRACE_EXECUTION From d740e6b777250dd9eae026f012714027c62d7ee9 Mon Sep 17 00:00:00 2001 From: Gianluca Goti Date: Tue, 23 Aug 2022 21:34:53 +0200 Subject: [PATCH 3/7] Bugfix tb_top.sv --- RI5CY-sameIF/tb/core/tb_top.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/RI5CY-sameIF/tb/core/tb_top.sv b/RI5CY-sameIF/tb/core/tb_top.sv index 274fbcc..82bd983 100644 --- a/RI5CY-sameIF/tb/core/tb_top.sv +++ b/RI5CY-sameIF/tb/core/tb_top.sv @@ -34,7 +34,6 @@ module tb_top `endif - // comment to record execution trace //`define TRACE_EXECUTION @@ -148,6 +147,10 @@ module tb_top $readmemh(firmware, riscv_wrapper_i.ram_i.dp_ram_i.mem); + + $display("Display localparam value = 0x%0d", MEM_MODE); + + /////////////////////////// // Racetrack memory initialization /////////////////////////// From 0a09aa6d6c99535b3fed812398a89312bf8d4e2d Mon Sep 17 00:00:00 2001 From: Gianluca Goti Date: Tue, 23 Aug 2022 21:54:01 +0200 Subject: [PATCH 4/7] Bugfix tb_top.sv --- RI5CY-sameIF/tb/core/tb_top.sv | 3 --- 1 file changed, 3 deletions(-) diff --git a/RI5CY-sameIF/tb/core/tb_top.sv b/RI5CY-sameIF/tb/core/tb_top.sv index 82bd983..bb83209 100644 --- a/RI5CY-sameIF/tb/core/tb_top.sv +++ b/RI5CY-sameIF/tb/core/tb_top.sv @@ -146,9 +146,6 @@ module tb_top $time, firmware); $readmemh(firmware, riscv_wrapper_i.ram_i.dp_ram_i.mem); - - - $display("Display localparam value = 0x%0d", MEM_MODE); /////////////////////////// From 1f52d4d24bd166af461114a9bf0b83629c5a02bd Mon Sep 17 00:00:00 2001 From: Gianluca Goti Date: Wed, 24 Aug 2022 17:44:20 +0200 Subject: [PATCH 5/7] Updated pipelne file --- .gitlab-ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 75f98e3..073bc49 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -9,7 +9,7 @@ build_vsim_mem_std_mode0: - git submodule update --remote RI5CY-sameIF/rtl/fpnew - cd RI5CY-sameIF/tb/core - source /eda/scripts/init_questa_core_prime - - make RISCV_LIB=/opt/riscv-rv32ima-ilp32 MEM_MODE=0 MEM_TYPE=STD_MEM custom-vsim-run + - make RISCV_LIB=/opt/riscv-rv32ima-ilp32 MEM_MODE=MODE_0 MEM_TYPE=STD_MEM custom-vsim-run #build_vcs_lim_mem: # stage: vcs_lim_mem From 0ee55c7fd875c240f06606dfef809bcb52ec6328 Mon Sep 17 00:00:00 2001 From: Gianluca Goti Date: Mon, 29 Aug 2022 21:24:29 +0200 Subject: [PATCH 6/7] Updated README file with MEM_MODE instructions --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index b0061c8..6b698a9 100644 --- a/README.md +++ b/README.md @@ -50,9 +50,9 @@ Available memories: - Standard memory with LiM functionalities (LIM_MEM) - Racetrack memory with LiM functionalities (RT_LIM_MEM) -Racetrack memory supports two different modes, set the correct parameter `MEM_MODE` in file `RI5CY-sameIF/tb/core/tb_tob.sv` to choose the wanted configuration: -- Memory mode (MEM_MODE = 0) -- LiM mode (MEM_MODE = 1) +Racetrack memory supports two different modes, modify variable `MEM_MODE` inside the Makefile to choose the wanted configuration: +- Memory mode (MEM_MODE = MODE_0) +- LiM mode (MEM_MODE = MODE_1) From 35b604ce9c1d88580610410900afddf861c0724a Mon Sep 17 00:00:00 2001 From: Gianluca Goti Date: Mon, 29 Aug 2022 21:27:07 +0200 Subject: [PATCH 7/7] Updated README --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 6b698a9..cf0ee7e 100644 --- a/README.md +++ b/README.md @@ -46,9 +46,9 @@ Enter the directory `RI5CY-sameIF/tb/core` and modify the Makefile. In particula Modify variable `MEM_TYPE` inside the Makefile to build the desired memory type. Available memories: -- Standard memory (STD_MEM) -- Standard memory with LiM functionalities (LIM_MEM) -- Racetrack memory with LiM functionalities (RT_LIM_MEM) +- Standard memory (MEM_TYPE = STD_MEM) +- Standard memory with LiM functionalities (MEM_TYPE = LIM_MEM) +- Racetrack memory with LiM functionalities (MEM_TYPE = RT_LIM_MEM) Racetrack memory supports two different modes, modify variable `MEM_MODE` inside the Makefile to choose the wanted configuration: - Memory mode (MEM_MODE = MODE_0)