simh_diff_summary.md

Known differences between SimH, 11/70, and w11a

The SimH simulator focuses on the behavior that is relevant to the normal operation of operating systems and user code. Model differences that are operation relevant, e.g. in probe routines or model-dependent kernel routines, are handled correctly epending on the set cpu configuration. However, many model variations that do not effect normal operation are not modeled for performance reasons. In these cases, the J11 behavior is often used for all PDP-11 models, and also when set cpu 11/70 is configured.

Test codes are sometimes sensitive to those details, so the most relevant ones are listed here:

• instruction behavior
  • SimH: SPL doesn't have 11/70 behavior
  • SimH: State of N and Z and registers after a DIV abort with V=1
  • SimH: JSR SP pushes modified SP value
• stack limit and stack error behavior
  • SimH: stack limit check and addressing modes
  • SimH: stack limit check and vector push aborts
  • SimH: Red stack zone PSW protection
  • SimH: CPUERR.rsv has J11 behavior
  • SimH: No unconditional instruction fetch after stack error abort
• instruction abort handling
  • SimH: condition codes are not always unchanged after an abort
• service order and trap handling
  • SimH: trap and interrupt service order has J11 behavior
  • SimH: traced WAIT has J11 behavior
  • SimH: traced RTI/RTT that clears tbit does trap
  • SimH: vector flow that sets tbit does not trap
• memory management behavior
  • SimH: MMR1 recording has J11 behavior
  • SimH: MMU traps not suppressed when MMU register accessed
  • SimH: The 'instruction completed flag' in MMR0 is not implemented
  • SimH: MMU aborts have priority over NXM aborts
• not implemented 11/70 features
  • SimH: 18-bit UNIBUS address space not mapped
  • SimH: MMU maintenance mode not implemented