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updated verilog and documentation
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wulffern committed Jul 4, 2024
1 parent d984a8f commit 670e460
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4 changes: 4 additions & 0 deletions docs/info.md
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Expand Up @@ -124,7 +124,11 @@ Navigate to the testbench and run a typical simulation (requires cicsim)
```bash
cd ip/tt06_sar_sky130nm/sim/TT06_SAR
make typical OPT="Debug"
cicsim wave output_tran/tran_DebugLayGtKttTtVt.raw
```
The interesting signals are `v(xdut.sunsar_sar8b_cv_0.sarn)` and
`v(xdut.sunsar_sar8b_cv_0.sarp)` which are the top plates of the CDAC. The
inputs to the SAR is `v(ua[0])` and `v(ua[1])`.

The main testbench is `ip/tt06_sar_sky130nm/sim/TT6_06/tran.spi`

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77 changes: 35 additions & 42 deletions src/project.v
Original file line number Diff line number Diff line change
Expand Up @@ -21,18 +21,41 @@ module tt_um_TT06_SAR_wulffern (
input wire rst_n
);

parameter OFF = 0,
SAMPLE = 1,
CONVERT = 2,
DONE=3;
logic [1:0] state;
logic [1:0] next_state;

logic [7:0] dout;
logic [7:0] sampled_dout;
logic done;
logic tie_l =0;
logic tie_h = 1;


assign uo_out = sampled_dout;
assign uio_out[0] = done;

assign uio_out[1] = tie_l;
assign uio_out[2] = tie_l;
assign uio_out[3] = tie_l;
assign uio_out[4] = tie_l;
assign uio_out[5] = tie_l;
assign uio_out[6] = tie_l;
assign uio_out[7] = tie_l;
assign uio_oe[0] = tie_h;
assign uio_oe[1] = tie_l;
assign uio_oe[2] = tie_l;
assign uio_oe[3] = tie_l;
assign uio_oe[4] = tie_l;
assign uio_oe[5] = tie_l;
assign uio_oe[6] = tie_l;
assign uio_oe[7] = tie_l;


//State machine, combinatorial part
parameter OFF = 0,
SAMPLE = 1,
CONVERT = 2,
DONE=3;
logic [1:0] state;
logic [1:0] next_state;
always_comb begin
case (state)
OFF: begin
Expand All @@ -58,35 +81,11 @@ module tt_um_TT06_SAR_wulffern (
real lsb = 1.0/64.0;
`else
logic tmp;

`endif

assign uo_out = sampled_dout;
assign uio_out[0] = done;

assign uio_out[1] = tie_l;
assign uio_out[2] = tie_l;
assign uio_out[3] = tie_l;
assign uio_out[4] = tie_l;
assign uio_out[5] = tie_l;
assign uio_out[6] = tie_l;
assign uio_out[7] = tie_l;
assign uio_oe[0] = tie_h;
assign uio_oe[1] = tie_l;
assign uio_oe[2] = tie_l;
assign uio_oe[3] = tie_l;
assign uio_oe[4] = tie_l;
assign uio_oe[5] = tie_l;
assign uio_oe[6] = tie_l;
assign uio_oe[7] = tie_l;


//always #5 iclk = !iclk;
//& ~done & ui_in[0];


//Main SAR loop
always_ff @(posedge clk or negedge clk) begin

if(~ui_in[0]) begin
state <= OFF;
tmp = 0;
Expand All @@ -101,7 +100,7 @@ module tt_um_TT06_SAR_wulffern (
end// !`ifdef ANA_TYPE_REAL
else if(clk == 0) begin
state = CONVERT;
`ifdef ANA_TYPE_REAL
`ifdef ANA_TYPE_REAL
smpl = ua_0 - ua_1;
tmp = smpl;

Expand All @@ -121,27 +120,21 @@ module tt_um_TT06_SAR_wulffern (
dout[i] = 0;
end
end
`else
`else
if(tmp == 0) begin
dout[7] <= 1;
dout[7] <= 1;
tmp <= 1;

end
else begin
dout[7] <= 0;
dout[7] <= 0;
tmp = 0;
end
`endif
`endif

end

state = next_state;
end // else: !if(~ui_in[0])





end // always_ff @ (posedge clk)

always @(posedge done) begin
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47 changes: 21 additions & 26 deletions src/tb_ana.v
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Expand Up @@ -2,10 +2,10 @@
`timescale 1 ns / 1 ps
module test;

logic rst_n = 0;
logic rst_n = 0;

logic clk = 0;
always #125 clk = !clk;
logic clk = 0;
always #125 clk = !clk;

logic VGND;
logic VPWR;
Expand All @@ -15,20 +15,18 @@ module test;
logic [7:0] uio_in;
logic [7:0] uio_out;
logic [7:0] uio_oe;
wire ena;


`ifdef ANA_TYPE_REAL
real ua_0 = 0;
real ua_1 = 0;
real ua_0 = 0;
real ua_1 = 0;

`else
tri [7:0] ua;
logic uain = 0;
tri [7:0] ua;
logic uain = 0;
assign ua = uain;
`endif
wire ena;



tt_um_TT06_SAR_wulffern dut (
.VGND(VGND),
.VPWR(VPWR),
Expand All @@ -50,34 +48,31 @@ module test;


`ifdef ANA_TYPE_REAL


always #100 begin
ua_0 = $sin(2*3.14*1/7750*$time);
ua_1 = -$sin(2*3.14*1/7750*$time);
end

`endif



initial
begin
$dumpfile("test.vcd");
$dumpvars(0,test);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,test);

ui_in = 0;
ui_in = 0;


#10 rst_n = 0;
#10 rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;

#10 VGND = 0;
#1 VPWR = 1;
#10 VGND = 0;
#1 VPWR = 1;

#500 ui_in[0] = 1;
#500 ui_in[0] = 1;

#5000 $stop;
#5000 $stop;

end
end
endmodule // test

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