Play with my AX7021, Mizar_Z7020, AXU2CGB boards.
axis components split and combine
The Video Frame Buffer IP study
TPG --> CSI-TX --> CSI-RX
cmos->vid_in->swich->vdma->ddr->resize/crop/pan/etc..->vdma->vid_out on AX7021
cmos->vid_in->isp(here?)->swich->vdma->?->ddr->resize/crop/pan/etc..->vdma->vid_out on AX7021
vpss pip
a Crop/PIP IP using HLS
linux config isp and ...
microblaze implements on Microphase board(Artix-7)
edid