SystemVerilog Solutions to Exercise from HDLBits
English | 中文
As the title said, this is a personal set of solutions to HDL programming.
Well, I want to try SystemVerilog in my programming.
Why SystemVerilog?
- Embracing newer tech: SystemVerilog is the superset of Verilog HDL, and it's more expressive and easier to program than Verilog HDL.
- SystemVerilog is friendly for testing/verification.
- It's supported to upload
.sv
sources to HDLBits directly.
All source files of HDL(e.g. SystemVerilog) would follow this style(in template.sv):
// Date: YYYY-MM-DD
// Author: Stephen Zhang
// URL: the url to the question
/** Question:
* <descrpition of question>
*/
module top_module
(
input logic in,
output logic out
);
assign out = ~in;
endmodule
// EOF
And English is preferred as the main language of document/comments.